[all-commits] [llvm/llvm-project] b49f8f: AMDGPU/GlobalISel: add RegBankLegalize rules for b...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/shifts
  Home:   https://github.com/llvm/llvm-project
  Commit: b49f8fab24145e734c7c69e1299f10065bc7e5a8
      https://github.com/llvm/llvm-project/commit/b49f8fab24145e734c7c69e1299f10065bc7e5a8
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-05-26 (Mon, 26 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg

Uniform S16 shifts have to be extended to S32 using appropriate Extend
before lowering to S32 instruction.
Uniform packed V2S16 are lowered to SGPR S32 instructions,
other option is to use VALU packed V2S16 and ReadAnyLane.
For uniform S32 and S64 and divergent S16, S32, S64 and V2S16 there are
instructions available.



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