[all-commits] [llvm/llvm-project] f4ded8: AMDGPU/GlobalISel: add RegBankLegalize rules for A...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/andorxor
  Home:   https://github.com/llvm/llvm-project
  Commit: f4ded85aeae7517fd05265634fad438bb4d515a2
      https://github.com/llvm/llvm-project/commit/f4ded85aeae7517fd05265634fad438bb4d515a2
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-05-26 (Mon, 26 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR

Uniform S1 is lowered to S32.
Divergent S1 is selected as VCC(S1) instruction select will select
SALU instruction based on wavesize (S32 or S64).
S16 are selected as is. There are register classes for vgpr S16.
Since some isel patterns check for sgpr S16 we don't lower to S32.
For 32 and 64 bit types we use B32/B64 rules that cover scalar vector
and pointers types.
SALU B32 and B64 and VALU B32 instructions are available.
Divergent B64 is lowered to B32.



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