[all-commits] [llvm/llvm-project] 971615: AMDGPU/GlobalISel: add RegBankLegalize rules for e...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/extends
  Home:   https://github.com/llvm/llvm-project
  Commit: 97161545fc7d53077ec52f9b6abdcc5caf78fff9
      https://github.com/llvm/llvm-project/commit/97161545fc7d53077ec52f9b6abdcc5caf78fff9
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-05-26 (Mon, 26 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc

Uniform S1:
Truncs to uniform S1 and AnyExts from S1 are left as is as they are meant
to be combined away. Uniform S1 ZExt and SExt are lowered using select.
Divergent S1:
Trunc of VGPR to VCC is lowered as compare.
Extends of VCC are lowered using select.

For remaining types:
S32 to S64 ZExt and SExt are lowered using merge values, AnyExt and Trunc
are again left as is to be combined away.
Notably uniform S16 for SExt and Zext is not lowered to S32 and left as is
for instruction select to deal with them. This is because there are patterns
that check for S16 type.



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