[all-commits] [llvm/llvm-project] 53393e: [LoongArch] Prevent R0/R1 allocation for rj operan...

[hev via All-commits]

  Branch: refs/heads/release/20.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 53393e26d5f4e93c88c4c1fb737b30658de49992
      https://github.com/llvm/llvm-project/commit/53393e26d5f4e93c88c4c1fb737b30658de49992
  Author: hev <wangrui at loongson.cn>
  Date:   2025-05-23 (Fri, 23 May 2025)

  Changed paths:
    M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
    M llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchLVZInstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
    A llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll

  Log Message:
  -----------
  [LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG (#140862)

The `[G]CSRXCHG` instruction must not use R0 or R1 as the `rj` operand,
as encoding `rj` as 0 or 1 will be interpreted as `[G]CSRRD` OR
`[G]CSRWR`, respectively, rather than `[G]CSRXCHG`.

This patch introduces a new register class `GPRNoR0R1` and updates the
`[G]CSRXCHG` instruction definition to use it for the `rj` operand,
ensuring the register allocator avoids assigning R0 or R1.

Fixes #140842

(cherry picked from commit bd8578c3574d77bc1231f047bced4a0053a1b000)



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