[all-commits] [llvm/llvm-project] 52c2e4: [NFC][CodeGen] Adopt MachineFunctionProperties con...

[Rahul Joshi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 52c2e45c11ee37d8efcf87cbfa5c9f23cbdd566b
      https://github.com/llvm/llvm-project/commit/52c2e45c11ee37d8efcf87cbfa5c9f23cbdd566b
  Author: Rahul Joshi <rjoshi at nvidia.com>
  Date:   2025-05-23 (Fri, 23 May 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/PeepholeOptimizer.h
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
    M llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
    M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
    M llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
    M llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
    M llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.h
    M llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
    M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.h
    M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
    M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
    M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
    M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
    M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
    M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
    M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
    M llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
    M llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
    M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
    M llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonGenMux.cpp
    M llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
    M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
    M llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
    M llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
    M llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp
    M llvm/lib/Target/M68k/M68kExpandPseudo.cpp
    M llvm/lib/Target/MSP430/MSP430BranchSelector.cpp
    M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
    M llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
    M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
    M llvm/lib/Target/Mips/MipsExpandPseudo.cpp
    M llvm/lib/Target/Mips/MipsMulMulBugPass.cpp
    M llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
    M llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
    M llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
    M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
    M llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
    M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
    M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
    M llvm/lib/Target/Sparc/DelaySlotFiller.cpp
    M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
    M llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
    M llvm/lib/Target/X86/X86CmovConversion.cpp
    M llvm/lib/Target/X86/X86CompressEVEX.cpp
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FastTileConfig.cpp
    M llvm/lib/Target/X86/X86FixupBWInsts.cpp
    M llvm/lib/Target/X86/X86FixupInstTuning.cpp
    M llvm/lib/Target/X86/X86FixupLEAs.cpp
    M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
    M llvm/lib/Target/X86/X86FloatingPoint.cpp
    M llvm/lib/Target/X86/X86PadShortFunction.cpp
    M llvm/lib/Target/X86/X86TileConfig.cpp
    M llvm/lib/Target/X86/X86VZeroUpper.cpp
    M llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
    M llvm/tools/llvm-exegesis/lib/Assembler.cpp
    M llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
    M llvm/unittests/MI/LiveIntervalTest.cpp
    M llvm/unittests/MIR/MachineMetadata.cpp
    M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

  Log Message:
  -----------
  [NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)



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