[all-commits] [llvm/llvm-project] 62cae9: [AArch64] Don't use LowerToPredicatedOp to shuffle...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62cae9c3de6250476fe0937a4a184b6245ca9c95
      https://github.com/llvm/llvm-project/commit/62cae9c3de6250476fe0937a4a184b6245ca9c95
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-05-23 (Fri, 23 May 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll

  Log Message:
  -----------
  [AArch64] Don't use LowerToPredicatedOp to shufflevector -> SVE lowerings (#140713)

The use of `LowerToPredicatedOp` here seems like a mistake as
`LowerToPredicatedOp` turns the SDValue passed to it into the desired
predicated node by copying over operands (and adding a predicate). This
results in two odd things here, the BITCASTs created and passed to
`LowerToPredicatedOp` are not used, only the operands of those bitcasts
are taken. Secondly, when a shuffle vector node is passed directly to
`LowerToPredicatedOp` to create a `REVD_MERGE_PASSTHRU` node an invalid
REV node is created as REV only takes one vector operand, but both
operands from the shuffle vector are copied to the new REV node. This is
not an issue in practice as the extra operand is ignored.

These issues were found by the verification added in #140472.

Part of #140472.

Note: Test changes only result in the vxf64 lowering matching the vxi64
lowering.



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