[all-commits] [llvm/llvm-project] 3ef1b0: [RISCV] add Double Trap extension requires Zicsr (...

[Jerry Zhang Jian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ef1b07a6ce759d5036ccaa78f0e4512528964c6
      https://github.com/llvm/llvm-project/commit/3ef1b07a6ce759d5036ccaa78f0e4512528964c6
  Author: Jerry Zhang Jian <jerry.zhangjian at sifive.com>
  Date:   2025-05-23 (Fri, 23 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] add Double Trap extension requires Zicsr (#141016)

- The double trap extension requires `mtval2' register, so add Zicsr as
required extension

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian at sifive.com>



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications