[all-commits] [llvm/llvm-project] 569b6f: [RISCV] Add Andes A25/AX25 processor definition (#...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 569b6f6dade6a1a1b758d982bcd9d91abafb787f
      https://github.com/llvm/llvm-project/commit/569b6f6dade6a1a1b758d982bcd9d91abafb787f
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-05-22 (Thu, 22 May 2025)

  Changed paths:
    A clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
    A clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Andes A25/AX25 processor definition (#140681)

Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that
implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are
developed by Andes Technology https://www.andestech.com, a RISC-V IP
provider.

The overviews for A25/AX25:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/

Scheduling model will be implemented in a later PR.



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