[all-commits] [llvm/llvm-project] 60ad6e: [SelectionDAG][RISCV] Use VP_LOAD to widen MLOAD i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 60ad6e3fa45c03dc1fc7521ead7583a9a7d9fb61
      https://github.com/llvm/llvm-project/commit/60ad6e3fa45c03dc1fc7521ead7583a9a7d9fb61
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-21 (Wed, 21 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    A llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Use VP_LOAD to widen MLOAD in type legalization when possible. (#140595)

Padding the mask using 0 elements doesn't work for scalable vectors. Use
VP_LOAD and change the VL instead.

This fixes crash for Zve32x. Test file was split since i64 isn't a valid
element type for Zve32x.

Fixes #140198.



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