[all-commits] [llvm/llvm-project] 76c9bf: [NVPTX] Remove Float register classes (#140487)

Wed May 21 11:34:20 PDT 2025

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76c9bfefa416f66a3fe79164874e13a612e00415
      https://github.com/llvm/llvm-project/commit/76c9bfefa416f66a3fe79164874e13a612e00415
  Author: Alex MacLean <amaclean at nvidia.com>
  Date:   2025-05-21 (Wed, 21 May 2025)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
    M llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
    M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
    M llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
    M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
    M llvm/test/CodeGen/NVPTX/access-non-generic.ll
    M llvm/test/CodeGen/NVPTX/aggregate-return.ll
    M llvm/test/CodeGen/NVPTX/and-or-setcc.ll
    M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
    M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
    M llvm/test/CodeGen/NVPTX/atomics.ll
    M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
    M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
    M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/bug22322.ll
    M llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
    M llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
    M llvm/test/CodeGen/NVPTX/convert-fp.ll
    M llvm/test/CodeGen/NVPTX/convert-sm100.ll
    M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
    M llvm/test/CodeGen/NVPTX/convert-sm80.ll
    M llvm/test/CodeGen/NVPTX/convert-sm90.ll
    M llvm/test/CodeGen/NVPTX/copysign.ll
    M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
    M llvm/test/CodeGen/NVPTX/div.ll
    M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
    M llvm/test/CodeGen/NVPTX/f16-abs.ll
    M llvm/test/CodeGen/NVPTX/f16-instructions.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/f32-ex2.ll
    M llvm/test/CodeGen/NVPTX/f32-lg2.ll
    M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
    M llvm/test/CodeGen/NVPTX/fexp2.ll
    M llvm/test/CodeGen/NVPTX/flog2.ll
    M llvm/test/CodeGen/NVPTX/fma-assoc.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
    M llvm/test/CodeGen/NVPTX/fma.ll
    M llvm/test/CodeGen/NVPTX/fp-contract.ll
    M llvm/test/CodeGen/NVPTX/fp-literals.ll
    M llvm/test/CodeGen/NVPTX/frem.ll
    M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
    M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
    M llvm/test/CodeGen/NVPTX/inline-asm.ll
    M llvm/test/CodeGen/NVPTX/intrinsics.ll
    M llvm/test/CodeGen/NVPTX/ld-generic.ll
    M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
    M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
    M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
    M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
    M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
    M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
    M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
    M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
    M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
    M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
    M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
    M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
    M llvm/test/CodeGen/NVPTX/math-intrins.ll
    M llvm/test/CodeGen/NVPTX/misched_func_call.ll
    M llvm/test/CodeGen/NVPTX/param-add.ll
    M llvm/test/CodeGen/NVPTX/param-load-store.ll
    M llvm/test/CodeGen/NVPTX/param-overalign.ll
    M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
    M llvm/test/CodeGen/NVPTX/rcp-opt.ll
    M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
    M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
    M llvm/test/CodeGen/NVPTX/reg-types.ll
    M llvm/test/CodeGen/NVPTX/shfl-p.ll
    M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
    M llvm/test/CodeGen/NVPTX/shfl.ll
    M llvm/test/CodeGen/NVPTX/st-addrspace.ll
    M llvm/test/CodeGen/NVPTX/st-generic.ll
    M llvm/test/CodeGen/NVPTX/st-param-imm.ll
    M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
    M llvm/test/CodeGen/NVPTX/surf-read.ll
    M llvm/test/CodeGen/NVPTX/surf-tex.py
    M llvm/test/CodeGen/NVPTX/tag-invariant-loads.ll
    M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
    M llvm/test/CodeGen/NVPTX/tex-read.ll
    M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
    M llvm/test/CodeGen/NVPTX/vaargs.ll
    M llvm/test/CodeGen/NVPTX/variadics-backend.ll
    M llvm/test/CodeGen/NVPTX/vec-param-load.ll
    M llvm/test/CodeGen/NVPTX/vector-args.ll
    M llvm/test/CodeGen/NVPTX/vector-loads.ll
    M llvm/test/CodeGen/NVPTX/wmma.py
    M llvm/test/DebugInfo/NVPTX/debug-addr-class.ll
    M llvm/test/DebugInfo/NVPTX/debug-info.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
    M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

  Log Message:
  -----------
  [NVPTX] Remove Float register classes (#140487)

These classes are redundant, as the untyped "Int" classes can be used
for all float operations. This change is intended to be as minimal as
possible and leaves the many potential simplifications and refactors
this exposes as future work.

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