[all-commits] [llvm/llvm-project] f5cc36: [mlir][ROCDL] Add fp4 and fp6 conversion intrinsic...

[Krzysztof Drewniak via All-commits]

  Branch: refs/heads/users/krzysz00/mxfp-conversion-intrinsics
  Home:   https://github.com/llvm/llvm-project
  Commit: f5cc3663fb1045cc51a54f1c6ae3ff4a16ea4807
      https://github.com/llvm/llvm-project/commit/f5cc3663fb1045cc51a54f1c6ae3ff4a16ea4807
  Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
    M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp.mlir
    M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats.mlir
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs

This PR adds support for the scaled conversion intrinsics for fp4 and
fp6 types so that they can be targetted by a future amdgpu dialect op
or used directly.

Additionally, this patch refactors the copy-paste-heavy fp8 versions
of these scaled conversion intrinsics with tablegen `foreach` loops,
and fixes the fact that certain immargs weren't being stored as
attributes.

Note that some of the MLIR-level tests for those scaled fp8 intrinsics
had incorrect return types, which have been fixed.

(Note that while the operations have a known return type, the IR
format still prints that type for clarity).



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