[all-commits] [llvm/llvm-project] b3c329: [RISCV] Fix missing WriteRes for Q extensions in S...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b3c3297c1a8ee85efac7236b47883bc0b89d1883
      https://github.com/llvm/llvm-project/commit/b3c3297c1a8ee85efac7236b47883bc0b89d1883
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

  Log Message:
  -----------
  [RISCV] Fix missing WriteRes for Q extensions in SiFiveP800 scheudling model



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