[all-commits] [llvm/llvm-project] b92b54: [RISCV] Add scheduling model for SiFive P800 proce...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b92b548168ce6e9023b689cf0cf429dee62c3c0c
      https://github.com/llvm/llvm-project/commit/b92b548168ce6e9023b689cf0cf429dee62c3c0c
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/div.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/fmadd.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/load.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mask.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-cpop.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlse-vsse.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vmv.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbb.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbc.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkg.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkned.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksed.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksh.s

  Log Message:
  -----------
  [RISCV] Add scheduling model for SiFive P800 processors (#139316)

The scheduling model for SiFive P800 series cores. They have 6 integer
pipes, 2 floating point pipes, and 2 vector pipes.

https://chipsandcheese.com/p/hot-chips-2023-sifives-p870-takes-risc-v-further

The tests are meant to have the same coverage as its P600 counterpart.



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