[all-commits] [llvm/llvm-project] 09fd8f: [X86] matchBinaryPermuteShuffle - match AVX512 "cr...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 09fd8f0093b8ff489d76285d893be152e4ca4c24
      https://github.com/llvm/llvm-project/commit/09fd8f0093b8ff489d76285d893be152e4ca4c24
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll

  Log Message:
  -----------
  [X86] matchBinaryPermuteShuffle - match AVX512 "cross lane" SHLDQ/SRLDQ style patterns using VALIGN (#140538)

Very similar to what we do in lowerShuffleAsVALIGN

I've updated isTargetShuffleEquivalent to correctly handle SM_SentinelZero in the expected shuffle mask, but it only allows an exact match (or the test mask was undef) - it can't be used to match zero elements with MaskedVectorIsZero.

Noticed while working on #140516



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