[all-commits] [llvm/llvm-project] 5dfaf8: [LLVM][AArch64] Correctly lower funnel shifts by c...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5dfaf8418d6b597ef75cf768dba1cd26fc8b318c
      https://github.com/llvm/llvm-project/commit/5dfaf8418d6b597ef75cf768dba1cd26fc8b318c
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-05-20 (Tue, 20 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/fsh-combiner-disabled.ll

  Log Message:
  -----------
  [LLVM][AArch64] Correctly lower funnel shifts by constants. (#140058)

Prevent LowerFunnelShift from creating an invalid ISD::FSHR when
lowering "ISD::FSHL X, Y, 0". Such inputs are rare because it's a NOP
that DAGCombiner will optimise away. However, we should not rely on this
and so this PR mirrors the same optimisation.
    
Ensure LowerFunnelShift normalises constant shift amounts because isel
rules expect them to be in the range [0, src bit length).
    
NOTE: To simiplify testing, this PR also adds a command line option to
disable the DAG combiner (-combiner-disabled).



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