[all-commits] [llvm/llvm-project] 360184: AMDGPU: Check for subreg match when folding throug...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36018494fdb9e92e0f61f6937e5ecd3a4472677f
      https://github.com/llvm/llvm-project/commit/36018494fdb9e92e0f61f6937e5ecd3a4472677f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/operand-folding.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir

  Log Message:
  -----------
  AMDGPU: Check for subreg match when folding through reg_sequence (#140582)

We need to consider the use instruction's intepretation of the bits,
not the defined immediate without use context. This will regress
some cases where we previously coud match f64 inline constants. We
can restore them by either using pseudo instructions to materialize f64
constants, or recognizing reg_sequence decomposed into 32-bit pieces for them
(which essentially means recognizing every other input is a 0).

Fixes #139908



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