[all-commits] [llvm/llvm-project] d0ee35: Fix typo in IRDL docs (#140460)

Mon May 19 12:34:56 PDT 2025

  Branch: refs/heads/users/qinkunbao/spr/implement-srcsanitize-for-ubsan
  Home:   https://github.com/llvm/llvm-project
  Commit: d0ee35851bb9fca4ee6c53dc1cc081d999a95e65
      https://github.com/llvm/llvm-project/commit/d0ee35851bb9fca4ee6c53dc1cc081d999a95e65
  Author: Noam Zaks <63877260+noamzaks at users.noreply.github.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td

  Log Message:
  -----------
  Fix typo in IRDL docs (#140460)

Rename "can has" -> to "has".
And replace a "can have" with a "has" to make it explicit that something is required.

  Commit: 572add06012036366e02ff5fe6be8e0bd803b157
      https://github.com/llvm/llvm-project/commit/572add06012036366e02ff5fe6be8e0bd803b157
  Author: Timm Baeder <tbaeder at redhat.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M clang/lib/AST/ByteCode/Interp.cpp
    M clang/test/SemaCXX/consteval-assert.cpp

  Log Message:
  -----------
  [clang][bytecode] Diagnose failed constexpr assertions differently (#140000)

Adjust to the new way the ast walker is doing it.

  Commit: d067014f13871642888afde850cdc558c32f350c
      https://github.com/llvm/llvm-project/commit/d067014f13871642888afde850cdc558c32f350c
  Author: Liam Semeria <56208783+liamsemeria at users.noreply.github.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/include/llvm/ADT/APInt.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Support/APInt.cpp
    M llvm/unittests/ADT/APIntTest.cpp

  Log Message:
  -----------
  [APInt] Added APInt::clearBits() method (#137098)

Added APInt::clearBits(unsigned loBit, unsigned hiBit) that clears bits within a certain range.

Fixes #136550

---------

Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>

  Commit: 416b7dfaa0d114b552c596d320f0aaac5651e61e
      https://github.com/llvm/llvm-project/commit/416b7dfaa0d114b552c596d320f0aaac5651e61e
  Author: jeanPerier <jperier at nvidia.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M flang/include/flang/Optimizer/CodeGen/FIROpPatterns.h
    M flang/lib/Optimizer/CodeGen/CodeGen.cpp
    M flang/test/Fir/convert-to-llvm.fir
    M flang/test/Fir/copy-codegen.fir
    M flang/test/Fir/embox-char.fir
    M flang/test/Fir/embox-substring.fir

  Log Message:
  -----------
  [flang] use DataLayout instead of GEP to compute element size (#140235)

Now that the datalayout is part of codegen, use that to generate type
size constants in codegen instead of generating GEP.

  Commit: e8a307498d678970e0be8cd7718ba0779d5ee307
      https://github.com/llvm/llvm-project/commit/e8a307498d678970e0be8cd7718ba0779d5ee307
  Author: William <113542065+saturn691 at users.noreply.github.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M compiler-rt/lib/builtins/extendhfsf2.c
    M compiler-rt/lib/builtins/truncsfhf2.c

  Log Message:
  -----------
  [builtins][AArch32] Fix __gnu_* functions (#137638)

Move to a consistent calling convention for both Clang/GNU such that
they can be linked with each other.

All ARM targets now use the soft-float calling convention for
`__gnu_h2f_ieee` and `__gnu_f2h_ieee`, as described in
https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#the-floating-point-helper-functions.

  Commit: 70501ed2f0f9dc06baffa7ee124845e40687675b
      https://github.com/llvm/llvm-project/commit/70501ed2f0f9dc06baffa7ee124845e40687675b
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reduces-vf.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
    M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll

  Log Message:
  -----------
  [LoopVectorizer] Prune VFs based on plan register pressure (#132190)

This PR moves the register usage checking to after the plans are
created, so that any recipes that optimise register usage (such as
partial reductions) can be properly costed and not have their VF pruned
unnecessarily.

Depends on https://github.com/llvm/llvm-project/pull/137746

  Commit: 52e1995eca35da79d27576b94b614a7fd2420c41
      https://github.com/llvm/llvm-project/commit/52e1995eca35da79d27576b94b614a7fd2420c41
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll

  Log Message:
  -----------
  [X86] Add tests showing failure to combine AVX512 shuffles to match "cross lane" SHLDQ/SRLDQ patterns using VALIGN

We match two input shuffles, but not if one input is zero

  Commit: 992458d26bbd2b8744408dbb4ab8d6b6058301d6
      https://github.com/llvm/llvm-project/commit/992458d26bbd2b8744408dbb4ab8d6b6058301d6
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td

  Log Message:
  -----------
  [RISCV][NFC] Fix the mismatch in comment (#140511)

There should be only one `vector_in`.

And we remove the surrounding double quotes.

  Commit: 6d8a52146c853e74727d8f000dc6236781aa45dd
      https://github.com/llvm/llvm-project/commit/6d8a52146c853e74727d8f000dc6236781aa45dd
  Author: Bart Chrzaszcz <bartchr at google.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp

  Log Message:
  -----------
  [mlir] Fix bazel build after `c798e19`. (#140537)

`@llvm-project//mlir:LLVMDialect` builds fine without the header. Don't
think it was needed.

  Commit: c56e7f22f06ac52d2ef3ea487910ab60a1256138
      https://github.com/llvm/llvm-project/commit/c56e7f22f06ac52d2ef3ea487910ab60a1256138
  Author: Christian Sigg <csigg at google.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
    M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
    M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
    M mlir/test/Dialect/Arith/canonicalize.mlir

  Log Message:
  -----------
  [mlir][arith] Canonicalize sitofp(truncf) -> sitofp, and uitofp. (#139925)

Add a canonicalization patterns that simplifies `truncf(sitofp(x))` to
`sitofp(x)` and `truncf(uitofp(x))` to `uitofp(x)`, if truncf has default rounding mode.

This assumes that the destination type of truncf is representable by the
intermediate type.

Note that the truncf semantics requires that the destination type is
narrower than the source type, so this is true for all types I can
possibly think of, but one could probably construct an artificial
counter example.

Somewhat related: https://github.com/llvm/llvm-project/pull/128096

  Commit: 117144c6d977ee8f353af0dad2bde0cc887a29a0
      https://github.com/llvm/llvm-project/commit/117144c6d977ee8f353af0dad2bde0cc887a29a0
  Author: Qinkun Bao <qinkun at google.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M clang/lib/AST/ByteCode/Interp.cpp
    M clang/lib/Basic/NoSanitizeList.cpp
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp
    M clang/test/SemaCXX/consteval-assert.cpp
    M compiler-rt/lib/builtins/extendhfsf2.c
    M compiler-rt/lib/builtins/truncsfhf2.c
    M flang/include/flang/Optimizer/CodeGen/FIROpPatterns.h
    M flang/lib/Optimizer/CodeGen/CodeGen.cpp
    M flang/test/Fir/convert-to-llvm.fir
    M flang/test/Fir/copy-codegen.fir
    M flang/test/Fir/embox-char.fir
    M flang/test/Fir/embox-substring.fir
    M llvm/include/llvm/ADT/APInt.h
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Support/APInt.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reduces-vf.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
    M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll
    M llvm/unittests/ADT/APIntTest.cpp
    M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
    M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
    M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
    M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
    M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
    M mlir/test/Dialect/Arith/canonicalize.mlir

  Log Message:
  -----------
  remove braces for simple statements.

Created using spr 1.3.6

Compare: https://github.com/llvm/llvm-project/compare/df61d7a68cd4...117144c6d977

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