[all-commits] [llvm/llvm-project] 70501e: [LoopVectorizer] Prune VFs based on plan register ...

[Sam Tebbs via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 70501ed2f0f9dc06baffa7ee124845e40687675b
      https://github.com/llvm/llvm-project/commit/70501ed2f0f9dc06baffa7ee124845e40687675b
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reduces-vf.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
    M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll

  Log Message:
  -----------
  [LoopVectorizer] Prune VFs based on plan register pressure (#132190)

This PR moves the register usage checking to after the plans are
created, so that any recipes that optimise register usage (such as
partial reductions) can be properly costed and not have their VF pruned
unnecessarily.

Depends on https://github.com/llvm/llvm-project/pull/137746



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