[all-commits] [llvm/llvm-project] c78e6b: [RISCV] Add sext_inreg patterns for XAndesPerf nds...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c78e6bbd830a4633fa7c80aebb9680b6acf913c6
      https://github.com/llvm/llvm-project/commit/c78e6bbd830a4633fa7c80aebb9680b6acf913c6
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-05-19 (Mon, 19 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    A llvm/test/CodeGen/RISCV/rv32xandesperf.ll
    A llvm/test/CodeGen/RISCV/rv64xandesperf.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add sext_inreg patterns for XAndesPerf nds.bfos instruction (#139714)

Add the patterns sign_extend_inreg i1/i8/i16.



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