[all-commits] [llvm/llvm-project] 21c878: [AArch64][GlobalISel] Regenerate AArch64/GlobalISe...

David Green via All-commits all-commits at lists.llvm.org
Sat May 17 01:00:57 PDT 2025 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 21c878e72dddaa1495cb71ea636f69ddcab5e0f4
      https://github.com/llvm/llvm-project/commit/21c878e72dddaa1495cb71ea636f69ddcab5e0f4
  Author: David Green <david.green at arm.com>
  Date:   2025-05-17 (Sat, 17 May 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/artifact-combine-unmerge.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/artifact-find-value.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-shr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/labels-are-not-dead.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bzero.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaximum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminimum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp128-fconstant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-hint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-get-dynamic-area-offset.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-llround.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-lrint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-lround.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-with-debug-info.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fadd.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sbfx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ubfx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/phi-mir-debugify.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-rotate.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Regenerate AArch64/GlobalISel/*.mir test checks. NFC

This served as a test of update_mir_test_checks from #140296, although the test
changes are mostly because the tests have not ben regenerated in a long time.
We managed to stop it from removing extra comments, only the empty lines are
now removed.



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