[all-commits] [llvm/llvm-project] 8e53e3: Fix comment mentioning nonexistent parameter (#140...
Amir Ayupov via All-commits
all-commits at lists.llvm.org
Fri May 16 17:12:31 PDT 2025
Branch: refs/heads/users/aaupov/spr/bolt-support-pre-aggregated-basic-sample-profile
Home: https://github.com/llvm/llvm-project
Commit: 8e53e3b4ef79ad4f4658d6f3e235e49c6062aec5
https://github.com/llvm/llvm-project/commit/8e53e3b4ef79ad4f4658d6f3e235e49c6062aec5
Author: Matthias Braun <matze at braunis.de>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineOperand.h
Log Message:
-----------
Fix comment mentioning nonexistent parameter (#140138)
Don't mention nonexistent parameter in comment. The parameter was
removed in https://github.com/llvm/llvm-project/pull/126003 .
Commit: f113cab1912c19581a48b7330cadfbd24f51fc58
https://github.com/llvm/llvm-project/commit/f113cab1912c19581a48b7330cadfbd24f51fc58
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
Log Message:
-----------
[AMDGPU] Cleanup bytesel variables. NFC. (#140131)
Somehow we ended up with 2 sets of td variables: Is...ByteSel and
Has...ByteSel. Keep only Has... form.
Commit: 136f2ba2a7bca015ef831c91fb0db5e5e31b7632
https://github.com/llvm/llvm-project/commit/136f2ba2a7bca015ef831c91fb0db5e5e31b7632
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[Clang][AST] Fix HandleLValueBase to deal with references (#140105)
Since P2280R4 Unknown references and pointers was implemented,
HandleLValueBase now has to deal with referneces:
D.MostDerivedType->getAsCXXRecordDecl()
will return a nullptr if D.MostDerivedType is a ReferenceType. The fix
is to use getNonReferenceType() to obtain the Pointee Type if we have a
reference.
Fixes: https://github.com/llvm/llvm-project/issues/139452
Commit: 642d5d74b5cc8c07b0e35cfa24e8ffb7de189bcd
https://github.com/llvm/llvm-project/commit/642d5d74b5cc8c07b0e35cfa24e8ffb7de189bcd
Author: Nico Weber <thakis at chromium.org>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
A llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn] "port" fc7857ca95bb (CIRUnitTests)
CIRUnitTests depends on mlir, so create a dummy target to make
the sync script happy. (This is behind CLANG_ENABLE_CIR in cmake.)
Commit: 6d7b5c3742165d35100adc1605220b590c93ef89
https://github.com/llvm/llvm-project/commit/6d7b5c3742165d35100adc1605220b590c93ef89
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/wait.c
Log Message:
-----------
[OpenACC][CIR] Update tests after #140122
Patch #140122 changed the format of OpenACC 'async', without changing
the clang tests. This patch updates the test.
Commit: b07e19fe5d0521bf0652bd073a6cedc0c4984f2b
https://github.com/llvm/llvm-project/commit/b07e19fe5d0521bf0652bd073a6cedc0c4984f2b
Author: Thurston Dang <thurston at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
Log Message:
-----------
[NFCI][cfi] Refactor into 'SanitizerInfoFromCFICheckKind' (#140117)
This refactors existing code into a 'SanitizerInfoFromCFICheckKind'
helper function. This will be useful in future work to annotate CFI
checks with debug info
(https://github.com/llvm/llvm-project/pull/139809).
Commit: 5c25061f32c2d9a18fb8a35709a4b540f573aa89
https://github.com/llvm/llvm-project/commit/5c25061f32c2d9a18fb8a35709a4b540f573aa89
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[MLGO]{Github] Add MLGO docs page to the MLGO PR subscriber group
This ensures that the MLGO PR subscriber team gets pinged if the document gets
modified which makes sense given it is MLGO specific.
Commit: de0bcd0564e4e67ae2afe1bad41c7bc505362e19
https://github.com/llvm/llvm-project/commit/de0bcd0564e4e67ae2afe1bad41c7bc505362e19
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/stack-offset.ll
Log Message:
-----------
[RISCV] Use QC_E_ADDI while eliminating the frameindex (#139515)
The QC_E_ADDI instruction from the Xqcilia extension takes a signed
26-bit immediate and can be used instead of splitting the offset across
two ADDI's while eliminating the frameindex.
Commit: 8d3a70770fda43c1f1ae797f307adf25b65e7209
https://github.com/llvm/llvm-project/commit/8d3a70770fda43c1f1ae797f307adf25b65e7209
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Improve inline asm importer (#139989)
Add support for importing more information into InlineAsmOp:
elementtype, side effects, align stack, asm dialect and operand attrs.
Commit: 56aa935bec14116314ab0450be761ad9d776bfa8
https://github.com/llvm/llvm-project/commit/56aa935bec14116314ab0450be761ad9d776bfa8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/emit-encoded.h
M flang-rt/lib/runtime/edit-input.cpp
Log Message:
-----------
[flang-rt] Fix warnings
This patch fixes:
flang-rt/include/flang-rt/runtime/emit-encoded.h:67:27: error:
implicit conversion from 'const char16_t' to 'char32_t' may change
the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1114:18: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1133:18: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1033:14: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:986:14: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
Commit: 97ad399c48d33247a66cca928a77a612f1e7bb4d
https://github.com/llvm/llvm-project/commit/97ad399c48d33247a66cca928a77a612f1e7bb4d
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
A llvm/test/MC/AsmParser/token.s
Log Message:
-----------
MCParser: Move LCurly/RCurly testing into tokenIsStartOfStatement
Commit 8a0453e23abf27433b7539b2da2060d2df9fb39c (2015) added LCurly and
RCurly cases for Hexagon instruction bundles. While gas x86 also adopted
`{` in 2017 for pseudo prefixes (see `tc_symbol_chars`), `{` remains
uncommon among targets. Move `{` and `}` parsing into the newly
introduced `tokenIsStartOfStatement` hook (#137997).
Pull Request: https://github.com/llvm/llvm-project/pull/140101
Commit: f3f28323adbb9d01372d81b4c78ed94683e58757
https://github.com/llvm/llvm-project/commit/f3f28323adbb9d01372d81b4c78ed94683e58757
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
A llvm/include/llvm/ProfileData/DataAccessProf.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/DataAccessProf.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/unittests/ProfileData/CMakeLists.txt
A llvm/unittests/ProfileData/DataAccessProfTest.cpp
Log Message:
-----------
[StaticDataLayout][PGO] Add profile format for static data layout, and the classes to operate on the profiles. (#138170)
Context: For
https://discourse.llvm.org/t/rfc-profile-guided-static-data-partitioning/83744#p-336543-background-3,
we propose to profile memory loads and stores via hardware events,
symbolize the addresses of binary static data sections and feed the
profile back into compiler for data partitioning.
This change adds the profile format for static data layout, and the
classes to operate on it.
The profile and its format
1. Conceptually, a piece of data (call it a symbol) is represented by
its symbol name or its content hash. The former applies to majority of
data whose mangled name remains relatively stable over binary releases,
and the latter applies to string literals (with name patterns like
`.str.<N>[.llvm.<hash>]`.
- The symbols with samples are hot data. The number of hot symbols is
small relative to all symbols. The profile tracks its sampled counts and
locations. Sampled counts come from hardware events, and locations come
from debug information in the profiled binary. The symbols without
samples are cold data. The number of such cold symbols is large. The
profile tracks its representation (the name or content hash).
- Based on a preliminary study, debug information coverage for data
symbols is partial and best-effort. In the LLVM IR, global variables
with source code correspondence may or may not have debug information.
Therefore the location information is optional in the profiles.
2. The profile-and-compile cycle is similar to SamplePGO. Profiles are
sampled from production binaries, and used in next binary releases.
Known cold symbols and new hot symbols can both have zero sampled
counts, so the profile records known cold symbols to tell the two for
next compile.
In the profile's serialization format, strings are concatenated together
and compressed. Individual records stores the index.
A separate PR will connect this class to InstrProfReader/Writer via
MemProfReader/Writer.
---------
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 8d63afbe5c8c5856ab4c2e663c1076313001565d
https://github.com/llvm/llvm-project/commit/8d63afbe5c8c5856ab4c2e663c1076313001565d
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
M llvm/lib/MC/DXContainerRootSignature.cpp
M llvm/lib/ObjectYAML/DXContainerEmitter.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
Log Message:
-----------
[NFC] Refactoring MCDXBC to support out of order storage of root parameters (#137284)
This PR refactors mcdxbc data structure for root signatures to support
out of order storage of in memory root signature data.
closes: #139585
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: dae5c4e1e7deef1fddad6e83d0f109b6fc9c5cc4
https://github.com/llvm/llvm-project/commit/dae5c4e1e7deef1fddad6e83d0f109b6fc9c5cc4
Author: Iris Shi <0.0 at owo.li>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
Log Message:
-----------
[RISCV] Expand constant multiplication for targets without M extension (#137195)
Closes #137023
On RISC-V machines without a native multiply instruction (e.g., `rv32i`
base), multiplying a variable by a constant integer often compiles to a
call to a library routine like `__mul{s,d}i3`.
```assembly
.globl __mulxi3
.type __mulxi3, @function
__mulxi3:
mv a2, a0
mv a0, zero
.L1:
andi a3, a1, 1
beqz a3, .L2
add a0, a0, a2
.L2:
srli a1, a1, 1
slli a2, a2, 1
bnez a1, .L1
ret
```
This library function implements multiplication in software using a loop
of shifts and adds, processing the constant bit by bit. On rv32i, it
requires a minimum of 8 instructions (for multiply by `0`) and up to
about 200 instructions (by `0xffffffff`), involves heavy branching and
function call overhead.
When not optimizing for size, we could expand the constant
multiplication into a sequence of shift and add/sub instructions. For
now we use non-adjacent form for the shift and add/sub sequence, which
could save 1/2 - 2/3 instructions compared to a shl+add-only sequence.
Commit: 7028c00f69864d47e811f955d4b5cb54eaeb73ed
https://github.com/llvm/llvm-project/commit/7028c00f69864d47e811f955d4b5cb54eaeb73ed
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ProfileData/BUILD.gn
Log Message:
-----------
[gn build] Port f3f28323adbb
Commit: 13c484c6e1c96d44bcefe177ea96f170c2e3ac10
https://github.com/llvm/llvm-project/commit/13c484c6e1c96d44bcefe177ea96f170c2e3ac10
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR] Upstream Vector support in elementTypeIfVector (#140125)
Upstream vector support in the element type if vector as a required
change for upstreaming other Vec Ops
Issue https://github.com/llvm/llvm-project/issues/136487
Commit: 664c937b4378b4ecc12ac193f4205966a3aa2aac
https://github.com/llvm/llvm-project/commit/664c937b4378b4ecc12ac193f4205966a3aa2aac
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
Log Message:
-----------
[VPlan] Implement VPExtendedReduction, VPMulAccumulateReductionRecipe and corresponding vplan transformations. (#137746)
This patch introduce two new recipes.
* VPExtendedReductionRecipe
- cast + reduction.
* VPMulAccumulateReductionRecipe
- (cast) + mul + reduction.
This patch also implements the transformation that match following
patterns via vplan and converts to abstract recipes for better cost
estimation.
* VPExtendedReduction
- reduce(cast(...))
* VPMulAccumulateReductionRecipe
- reduce.add(mul(...))
- reduce.add(mul(ext(...), ext(...))
- reduce.add(ext(mul(ext(...), ext(...))))
The converted abstract recipes will be lower to the concrete recipes
(widen-cast + widen-mul + reduction) just before recipe execution.
Note that this patch still relies on legacy cost model the calculate the
cost for these patters.
Will enable vplan-based cost decision in #113903.
Split from #113903.
Commit: f95f3030e595b76a3aa0295997e7dcf865c28796
https://github.com/llvm/llvm-project/commit/f95f3030e595b76a3aa0295997e7dcf865c28796
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
Log Message:
-----------
[HLSL] Implicit resource binding for cbuffers (#139022)
Constant buffers defined with the `cbuffer` keyword do not have a
constructor. Instead, the call to initialize the resource handle based
on its binding is generated in codegen. This change adds initialization
of `cbuffer` handles that have implicit binding.
Closes #139617
Commit: 257dfc3a1f568218bf923f37e20a6aff862817b6
https://github.com/llvm/llvm-project/commit/257dfc3a1f568218bf923f37e20a6aff862817b6
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR] Fix using getElementType (#140177)
Fix for elementTypeIfVector
Commit: 9f438e0b0670d5d70fc81288a192b4e8815ac77a
https://github.com/llvm/llvm-project/commit/9f438e0b0670d5d70fc81288a192b4e8815ac77a
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
M llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
M llvm/test/MC/Mips/macro-rem.s
Log Message:
-----------
Mips,test: Fix check prefix
#140149
Commit: dc9171afc481f28865fc19ba7bc88c6596bb86e9
https://github.com/llvm/llvm-project/commit/dc9171afc481f28865fc19ba7bc88c6596bb86e9
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcibi.ll
Log Message:
-----------
[RISCV] Add isel patterns for generating Xqcibi branch instructions (#139872)
Add ISEL patterns for generating the Xqcibi branch immediate
instructions. Similar to #135771 adds new CondCodes for the various
branch instructions and uses them to return the appropriate instruction.
Commit: ca6398c79e43ea1289bfec8c623a55f47ed3f992
https://github.com/llvm/llvm-project/commit/ca6398c79e43ea1289bfec8c623a55f47ed3f992
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
A llvm/test/CodeGen/Mips/private-global-prefix.ll
Log Message:
-----------
[COFF][Mips] Set PrivateGlobalPrefix to .L (#140033)
When calling external functions which start with `L`, would generate
error: assembler label 'LeaveFoo' can not be undefined. This pr would
fix this issue.
Fix #134914.
Commit: 680b3b742da02972bc0b5298b6f472d2b95ca90a
https://github.com/llvm/llvm-project/commit/680b3b742da02972bc0b5298b6f472d2b95ca90a
Author: Iris Shi <0.0 at owo.li>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
Log Message:
-----------
[RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (#140003)
Followup of #139495 and #139508
Commit: 86e9be0954ac054bdf5164d1e9a17e330cbd2429
https://github.com/llvm/llvm-project/commit/86e9be0954ac054bdf5164d1e9a17e330cbd2429
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/include/llvm/ADT/EquivalenceClasses.h
Log Message:
-----------
EquivalenceClasses: Make ECValue public. NFC (#139689)
Expose the inner class so that we can explicitly write the type outside
the parent class.
Commit: 0eaaa1b2a096c005d6dd84d6f1bb7cea6d210828
https://github.com/llvm/llvm-project/commit/0eaaa1b2a096c005d6dd84d6f1bb7cea6d210828
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/docs/Heatmaps.md
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/wait.c
M clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M flang-rt/include/flang-rt/runtime/emit-encoded.h
M flang-rt/lib/runtime/edit-input.cpp
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
A llvm/include/llvm/ProfileData/DataAccessProf.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/MC/DXContainerRootSignature.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/ObjectYAML/DXContainerEmitter.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/DataAccessProf.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/CodeGen/Mips/private-global-prefix.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
A llvm/test/CodeGen/RISCV/xqcibi.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
A llvm/test/MC/AsmParser/token.s
M llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
M llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
M llvm/test/MC/Mips/macro-rem.s
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/unittests/ProfileData/CMakeLists.txt
A llvm/unittests/ProfileData/DataAccessProfTest.cpp
A llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ProfileData/BUILD.gn
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 882dde71c322722e28810d9123098f455cb554d8
https://github.com/llvm/llvm-project/commit/882dde71c322722e28810d9123098f455cb554d8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/docs/Heatmaps.md
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/Inputs/pre-aggregated-basic.txt
M bolt/test/X86/pre-aggregated-perf.test
M bolt/test/link_fdata.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/wait.c
M clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M flang-rt/include/flang-rt/runtime/emit-encoded.h
M flang-rt/lib/runtime/edit-input.cpp
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
A llvm/include/llvm/ProfileData/DataAccessProf.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/MC/DXContainerRootSignature.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/ObjectYAML/DXContainerEmitter.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/DataAccessProf.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/CodeGen/Mips/private-global-prefix.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
A llvm/test/CodeGen/RISCV/xqcibi.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
A llvm/test/MC/AsmParser/token.s
M llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
M llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
M llvm/test/MC/Mips/macro-rem.s
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/unittests/ProfileData/CMakeLists.txt
A llvm/unittests/ProfileData/DataAccessProfTest.cpp
A llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ProfileData/BUILD.gn
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
Fixed heatmap mode
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/5c513dcb2a61...882dde71c322
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