[all-commits] [llvm/llvm-project] 18ecff: [llvm] Use llvm::stable_sort (NFC) (#140067)
Qinkun Bao via All-commits
all-commits at lists.llvm.org
Fri May 16 08:15:17 PDT 2025
Branch: refs/heads/users/qinkunbao/spr/convert-specialcaselistsections-from-stringmap-to-vector-1
Home: https://github.com/llvm/llvm-project
Commit: 18ecff4f65067adfd9fcd721d93bb29b646e4756
https://github.com/llvm/llvm-project/commit/18ecff4f65067adfd9fcd721d93bb29b646e4756
Author: Kazu Hirata <kazu at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CGData/StableFunctionMapRecord.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVRange.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVReader.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVScope.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[llvm] Use llvm::stable_sort (NFC) (#140067)
Commit: 6033a4859a0131062bef4eb765b438e6110b40a2
https://github.com/llvm/llvm-project/commit/6033a4859a0131062bef4eb765b438e6110b40a2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/CodeGen/MIRPrinter.cpp
Log Message:
-----------
[CodeGen] Use std::tie to implement a comparison functor (NFC) (#140088)
std::tie simplifies the lexicographical comparison while making the
code a little more consistent within MIRPrinter.cpp as we have a very
similar comparison functor in MIRPrinter::convertCalledGlobals, about
30 lines below the code this patch touches.
Commit: f9dbfb1566043d744d66ff8b5415269c6ec59743
https://github.com/llvm/llvm-project/commit/f9dbfb1566043d744d66ff8b5415269c6ec59743
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenACC/acc-wait.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/test/Conversion/OpenACCToSCF/convert-openacc-to-scf.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[flang][acc] Update assembly formats to include asyncOnly, async, and wait (#140122)
The async implementation is inconsistent in terms of the assembly
format. While renaming `UpdateOp`'s `async` to `asyncOnly`, this PR
handles `asyncOnly` along with async operands in every operation.
Regarding `EnterDataOp` and `ExitDataOp`, they do not accept device
types; thus, the async and the wait clauses without values lead to the
`async` and the `wait` attributes (not `asyncOnly` nor `waitOnly`). This
PR also processes them with async and wait operands all together.
Commit: a6ddfb387df7866afc8ac0f7e9d517cd37345e61
https://github.com/llvm/llvm-project/commit/a6ddfb387df7866afc8ac0f7e9d517cd37345e61
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/DeclCXX.cpp
Log Message:
-----------
[NFC][Clang] Adopt simplified `getTrailingObjects` in DeclCXX (#140078)
- Adopt non-templated and ArrayRef returning forms of
`getTrailingObjects`.
- Replace some initialization loop with std::uninitialized_fill_n.
- Remove unneeded `numTrailingObjects` for last trailing type.
Commit: 6c405694d134f708c064df37bf4ac79a84374c58
https://github.com/llvm/llvm-project/commit/6c405694d134f708c064df37bf4ac79a84374c58
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Get type from start value for VPWidenIntOrFpInduction (NFC).
NFC for now but this can cause verification failures in the future,
since after bf5627c85e697 wide induction may be narrowed. By using the
type from the start value, we will always return the correct type.
Commit: acdba28e148ac1e94d6c041f9911230e1e90e9cd
https://github.com/llvm/llvm-project/commit/acdba28e148ac1e94d6c041f9911230e1e90e9cd
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.5.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-vs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/use-native-low-precision-1.ll
Log Message:
-----------
[DirectX] Set whole-module flags prior to evaluating per-function flags (#139967)
Fixes #139024 and #139954
- Refactor DXILShaderFlags to compute the flags that apply to a whole
module before computing flags that apply individually to each function
- Make DXILResourceMap const, since it is not modified in
DXILShaderFlags
- Per-function shader flag analysis now initially starts with the set of
flags that apply to the whole module instead of starting from no flags.
This change fixes the above linked issues
- Fix shader flag tests affected by the above change
Commit: 090f46d8d246762401c41c5486dde299382d6c90
https://github.com/llvm/llvm-project/commit/090f46d8d246762401c41c5486dde299382d6c90
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/include/clang/Sema/Overload.h
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
Log Message:
-----------
[Clang] Fix an assertion in the resolution of perfect matches (#140073)
Function pointers can have an identity conversion to a pointer to member
function if they are resolved to a member function.
Fix a regression introduced by #136203
Commit: efae492ad1ba80764ec4a85f5622a8713646f970
https://github.com/llvm/llvm-project/commit/efae492ad1ba80764ec4a85f5622a8713646f970
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
Log Message:
-----------
[VPlan] Add VPTypeAnalysis constructor taking a VPlan (NFC).
Add constructor that retrieves the scalar type from the trip count
expression, if no canonical IV is available. Used in the verifier, in
preparation for late verification, when the canonical IV has been
dissolved.
Commit: 4f663cca15f2b53c2bc6a84d1b1f5bd81679356d
https://github.com/llvm/llvm-project/commit/4f663cca15f2b53c2bc6a84d1b1f5bd81679356d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopPeel.cpp
Log Message:
-----------
[LoopPeel] Make sure PeelLast is always initialized.
Make sure PeelLast is initialized on all paths.
Should fix MSan bootstrap failures
https://lab.llvm.org/buildbot/#/builders/164/builds/9992
https://lab.llvm.org/buildbot/#/builders/94/builds/7158
Fixup after https://github.com/llvm/llvm-project/pull/139551.
Commit: fc7857ca95bba93807959ad09f983221db8811e1
https://github.com/llvm/llvm-project/commit/fc7857ca95bba93807959ad09f983221db8811e1
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
A clang/include/clang/CIR/Dialect/OpenACC/CIROpenACCTypeInterfaces.h
A clang/include/clang/CIR/Dialect/OpenACC/RegisterOpenACCExtensions.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenACC/CIROpenACCTypeInterfaces.cpp
A clang/lib/CIR/Dialect/OpenACC/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenACC/RegisterOpenACCExtensions.cpp
A clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/PointerLikeTest.cpp
M clang/unittests/CMakeLists.txt
Log Message:
-----------
[CIR] Add PointerLikeType interface support for cir::PointerType (#139768)
This adds code to attach the OpenACC PointerLikeType interface to
cir::PointerType, along with a unit test for the interface.
Commit: 2e6433b8293ac64923c737078e87dc39fc4bced6
https://github.com/llvm/llvm-project/commit/2e6433b8293ac64923c737078e87dc39fc4bced6
Author: Steven Perron <stevenperron at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
A clang/test/CodeGenHLSL/convergence/global_array.hlsl
Log Message:
-----------
[clang] Emit convergence tokens for loop in global array init (#140120)
When initializing a global array, a loop is generated, but no
convergence is emitted for the loop. This fixes that up.
Commit: a4eb0db062b646907a2c19d54f8240fe4bdd98ce
https://github.com/llvm/llvm-project/commit/a4eb0db062b646907a2c19d54f8240fe4bdd98ce
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/RootSignature.hlsl
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/lib/Frontend/HLSL/HLSLRootSignature.cpp
Log Message:
-----------
[HLSL][RootSignature] Add metadata generation for descriptor tables (#139633)
- prereq: Modify `RootSignatureAttr` to hold a reference to the owned
declaration
- Define and implement `MetadataBuilder` in `HLSLRootSignature`
- Integrate and invoke the builder in `CGHLSLRuntime.cpp` to generate
the Root Signature for any associated entry functions
- Add tests to demonstrate functionality in `RootSignature.hlsl`
Resolves https://github.com/llvm/llvm-project/issues/126584
Note: this is essentially just
https://github.com/llvm/llvm-project/pull/125131 rebased onto the new
approach of constructing a root signature decl, instead of holding the
elements in `AdditionalMembers`.
Commit: f01f08292e894a565baa1b2741b31fbcf53a18cb
https://github.com/llvm/llvm-project/commit/f01f08292e894a565baa1b2741b31fbcf53a18cb
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
Log Message:
-----------
AMDGPU: Make v2f32 -> v2f16 legal when target supports v_cvt_pk_f16_f32 (#139956)
If targets support v_cvt_pk_f16_f32 instruction, v2f32 -> v2f16 should
be legal. However, SelectionDAG does not allow us to specify the source
type in the legalization rules. To workaround this, we make FP_ROUND
Custom for v2f16 then set up v2f32 -> v2f16 to be legal during custom
lowering.
Fixes: SWDEV-532608 -- expected v_cvt_pk_f16_f32 was not generated.
Commit: a3c4a5cb63df01ae63ae0a8c3e4c3e1fdbc3b70c
https://github.com/llvm/llvm-project/commit/a3c4a5cb63df01ae63ae0a8c3e4c3e1fdbc3b70c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/docs/MLGO.rst
Log Message:
-----------
[MLGO][Docs] Add documentation on corpus tooling (#139362)
This adds some documentation on the three corpus tools, some examples,
and fixes the TODO telling me to get this done.
Commit: 8e53e3b4ef79ad4f4658d6f3e235e49c6062aec5
https://github.com/llvm/llvm-project/commit/8e53e3b4ef79ad4f4658d6f3e235e49c6062aec5
Author: Matthias Braun <matze at braunis.de>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineOperand.h
Log Message:
-----------
Fix comment mentioning nonexistent parameter (#140138)
Don't mention nonexistent parameter in comment. The parameter was
removed in https://github.com/llvm/llvm-project/pull/126003 .
Commit: f113cab1912c19581a48b7330cadfbd24f51fc58
https://github.com/llvm/llvm-project/commit/f113cab1912c19581a48b7330cadfbd24f51fc58
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
Log Message:
-----------
[AMDGPU] Cleanup bytesel variables. NFC. (#140131)
Somehow we ended up with 2 sets of td variables: Is...ByteSel and
Has...ByteSel. Keep only Has... form.
Commit: 136f2ba2a7bca015ef831c91fb0db5e5e31b7632
https://github.com/llvm/llvm-project/commit/136f2ba2a7bca015ef831c91fb0db5e5e31b7632
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[Clang][AST] Fix HandleLValueBase to deal with references (#140105)
Since P2280R4 Unknown references and pointers was implemented,
HandleLValueBase now has to deal with referneces:
D.MostDerivedType->getAsCXXRecordDecl()
will return a nullptr if D.MostDerivedType is a ReferenceType. The fix
is to use getNonReferenceType() to obtain the Pointee Type if we have a
reference.
Fixes: https://github.com/llvm/llvm-project/issues/139452
Commit: 642d5d74b5cc8c07b0e35cfa24e8ffb7de189bcd
https://github.com/llvm/llvm-project/commit/642d5d74b5cc8c07b0e35cfa24e8ffb7de189bcd
Author: Nico Weber <thakis at chromium.org>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
A llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn] "port" fc7857ca95bb (CIRUnitTests)
CIRUnitTests depends on mlir, so create a dummy target to make
the sync script happy. (This is behind CLANG_ENABLE_CIR in cmake.)
Commit: 6d7b5c3742165d35100adc1605220b590c93ef89
https://github.com/llvm/llvm-project/commit/6d7b5c3742165d35100adc1605220b590c93ef89
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/wait.c
Log Message:
-----------
[OpenACC][CIR] Update tests after #140122
Patch #140122 changed the format of OpenACC 'async', without changing
the clang tests. This patch updates the test.
Commit: b07e19fe5d0521bf0652bd073a6cedc0c4984f2b
https://github.com/llvm/llvm-project/commit/b07e19fe5d0521bf0652bd073a6cedc0c4984f2b
Author: Thurston Dang <thurston at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
Log Message:
-----------
[NFCI][cfi] Refactor into 'SanitizerInfoFromCFICheckKind' (#140117)
This refactors existing code into a 'SanitizerInfoFromCFICheckKind'
helper function. This will be useful in future work to annotate CFI
checks with debug info
(https://github.com/llvm/llvm-project/pull/139809).
Commit: 5c25061f32c2d9a18fb8a35709a4b540f573aa89
https://github.com/llvm/llvm-project/commit/5c25061f32c2d9a18fb8a35709a4b540f573aa89
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[MLGO]{Github] Add MLGO docs page to the MLGO PR subscriber group
This ensures that the MLGO PR subscriber team gets pinged if the document gets
modified which makes sense given it is MLGO specific.
Commit: de0bcd0564e4e67ae2afe1bad41c7bc505362e19
https://github.com/llvm/llvm-project/commit/de0bcd0564e4e67ae2afe1bad41c7bc505362e19
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/stack-offset.ll
Log Message:
-----------
[RISCV] Use QC_E_ADDI while eliminating the frameindex (#139515)
The QC_E_ADDI instruction from the Xqcilia extension takes a signed
26-bit immediate and can be used instead of splitting the offset across
two ADDI's while eliminating the frameindex.
Commit: 8d3a70770fda43c1f1ae797f307adf25b65e7209
https://github.com/llvm/llvm-project/commit/8d3a70770fda43c1f1ae797f307adf25b65e7209
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Improve inline asm importer (#139989)
Add support for importing more information into InlineAsmOp:
elementtype, side effects, align stack, asm dialect and operand attrs.
Commit: 56aa935bec14116314ab0450be761ad9d776bfa8
https://github.com/llvm/llvm-project/commit/56aa935bec14116314ab0450be761ad9d776bfa8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/emit-encoded.h
M flang-rt/lib/runtime/edit-input.cpp
Log Message:
-----------
[flang-rt] Fix warnings
This patch fixes:
flang-rt/include/flang-rt/runtime/emit-encoded.h:67:27: error:
implicit conversion from 'const char16_t' to 'char32_t' may change
the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1114:18: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1133:18: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:1033:14: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
flang-rt/lib/runtime/edit-input.cpp:986:14: error: implicit
conversion from 'char32_t' to 'char16_t' may lose precision and
change the meaning of the represented code unit
[-Werror,-Wcharacter-conversion]
Commit: 97ad399c48d33247a66cca928a77a612f1e7bb4d
https://github.com/llvm/llvm-project/commit/97ad399c48d33247a66cca928a77a612f1e7bb4d
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
A llvm/test/MC/AsmParser/token.s
Log Message:
-----------
MCParser: Move LCurly/RCurly testing into tokenIsStartOfStatement
Commit 8a0453e23abf27433b7539b2da2060d2df9fb39c (2015) added LCurly and
RCurly cases for Hexagon instruction bundles. While gas x86 also adopted
`{` in 2017 for pseudo prefixes (see `tc_symbol_chars`), `{` remains
uncommon among targets. Move `{` and `}` parsing into the newly
introduced `tokenIsStartOfStatement` hook (#137997).
Pull Request: https://github.com/llvm/llvm-project/pull/140101
Commit: f3f28323adbb9d01372d81b4c78ed94683e58757
https://github.com/llvm/llvm-project/commit/f3f28323adbb9d01372d81b4c78ed94683e58757
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
A llvm/include/llvm/ProfileData/DataAccessProf.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/DataAccessProf.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/unittests/ProfileData/CMakeLists.txt
A llvm/unittests/ProfileData/DataAccessProfTest.cpp
Log Message:
-----------
[StaticDataLayout][PGO] Add profile format for static data layout, and the classes to operate on the profiles. (#138170)
Context: For
https://discourse.llvm.org/t/rfc-profile-guided-static-data-partitioning/83744#p-336543-background-3,
we propose to profile memory loads and stores via hardware events,
symbolize the addresses of binary static data sections and feed the
profile back into compiler for data partitioning.
This change adds the profile format for static data layout, and the
classes to operate on it.
The profile and its format
1. Conceptually, a piece of data (call it a symbol) is represented by
its symbol name or its content hash. The former applies to majority of
data whose mangled name remains relatively stable over binary releases,
and the latter applies to string literals (with name patterns like
`.str.<N>[.llvm.<hash>]`.
- The symbols with samples are hot data. The number of hot symbols is
small relative to all symbols. The profile tracks its sampled counts and
locations. Sampled counts come from hardware events, and locations come
from debug information in the profiled binary. The symbols without
samples are cold data. The number of such cold symbols is large. The
profile tracks its representation (the name or content hash).
- Based on a preliminary study, debug information coverage for data
symbols is partial and best-effort. In the LLVM IR, global variables
with source code correspondence may or may not have debug information.
Therefore the location information is optional in the profiles.
2. The profile-and-compile cycle is similar to SamplePGO. Profiles are
sampled from production binaries, and used in next binary releases.
Known cold symbols and new hot symbols can both have zero sampled
counts, so the profile records known cold symbols to tell the two for
next compile.
In the profile's serialization format, strings are concatenated together
and compressed. Individual records stores the index.
A separate PR will connect this class to InstrProfReader/Writer via
MemProfReader/Writer.
---------
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 8d63afbe5c8c5856ab4c2e663c1076313001565d
https://github.com/llvm/llvm-project/commit/8d63afbe5c8c5856ab4c2e663c1076313001565d
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
M llvm/lib/MC/DXContainerRootSignature.cpp
M llvm/lib/ObjectYAML/DXContainerEmitter.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
Log Message:
-----------
[NFC] Refactoring MCDXBC to support out of order storage of root parameters (#137284)
This PR refactors mcdxbc data structure for root signatures to support
out of order storage of in memory root signature data.
closes: #139585
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: dae5c4e1e7deef1fddad6e83d0f109b6fc9c5cc4
https://github.com/llvm/llvm-project/commit/dae5c4e1e7deef1fddad6e83d0f109b6fc9c5cc4
Author: Iris Shi <0.0 at owo.li>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
Log Message:
-----------
[RISCV] Expand constant multiplication for targets without M extension (#137195)
Closes #137023
On RISC-V machines without a native multiply instruction (e.g., `rv32i`
base), multiplying a variable by a constant integer often compiles to a
call to a library routine like `__mul{s,d}i3`.
```assembly
.globl __mulxi3
.type __mulxi3, @function
__mulxi3:
mv a2, a0
mv a0, zero
.L1:
andi a3, a1, 1
beqz a3, .L2
add a0, a0, a2
.L2:
srli a1, a1, 1
slli a2, a2, 1
bnez a1, .L1
ret
```
This library function implements multiplication in software using a loop
of shifts and adds, processing the constant bit by bit. On rv32i, it
requires a minimum of 8 instructions (for multiply by `0`) and up to
about 200 instructions (by `0xffffffff`), involves heavy branching and
function call overhead.
When not optimizing for size, we could expand the constant
multiplication into a sequence of shift and add/sub instructions. For
now we use non-adjacent form for the shift and add/sub sequence, which
could save 1/2 - 2/3 instructions compared to a shl+add-only sequence.
Commit: 7028c00f69864d47e811f955d4b5cb54eaeb73ed
https://github.com/llvm/llvm-project/commit/7028c00f69864d47e811f955d4b5cb54eaeb73ed
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ProfileData/BUILD.gn
Log Message:
-----------
[gn build] Port f3f28323adbb
Commit: 13c484c6e1c96d44bcefe177ea96f170c2e3ac10
https://github.com/llvm/llvm-project/commit/13c484c6e1c96d44bcefe177ea96f170c2e3ac10
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR] Upstream Vector support in elementTypeIfVector (#140125)
Upstream vector support in the element type if vector as a required
change for upstreaming other Vec Ops
Issue https://github.com/llvm/llvm-project/issues/136487
Commit: 664c937b4378b4ecc12ac193f4205966a3aa2aac
https://github.com/llvm/llvm-project/commit/664c937b4378b4ecc12ac193f4205966a3aa2aac
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
Log Message:
-----------
[VPlan] Implement VPExtendedReduction, VPMulAccumulateReductionRecipe and corresponding vplan transformations. (#137746)
This patch introduce two new recipes.
* VPExtendedReductionRecipe
- cast + reduction.
* VPMulAccumulateReductionRecipe
- (cast) + mul + reduction.
This patch also implements the transformation that match following
patterns via vplan and converts to abstract recipes for better cost
estimation.
* VPExtendedReduction
- reduce(cast(...))
* VPMulAccumulateReductionRecipe
- reduce.add(mul(...))
- reduce.add(mul(ext(...), ext(...))
- reduce.add(ext(mul(ext(...), ext(...))))
The converted abstract recipes will be lower to the concrete recipes
(widen-cast + widen-mul + reduction) just before recipe execution.
Note that this patch still relies on legacy cost model the calculate the
cost for these patters.
Will enable vplan-based cost decision in #113903.
Split from #113903.
Commit: f95f3030e595b76a3aa0295997e7dcf865c28796
https://github.com/llvm/llvm-project/commit/f95f3030e595b76a3aa0295997e7dcf865c28796
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
Log Message:
-----------
[HLSL] Implicit resource binding for cbuffers (#139022)
Constant buffers defined with the `cbuffer` keyword do not have a
constructor. Instead, the call to initialize the resource handle based
on its binding is generated in codegen. This change adds initialization
of `cbuffer` handles that have implicit binding.
Closes #139617
Commit: 257dfc3a1f568218bf923f37e20a6aff862817b6
https://github.com/llvm/llvm-project/commit/257dfc3a1f568218bf923f37e20a6aff862817b6
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR] Fix using getElementType (#140177)
Fix for elementTypeIfVector
Commit: 9f438e0b0670d5d70fc81288a192b4e8815ac77a
https://github.com/llvm/llvm-project/commit/9f438e0b0670d5d70fc81288a192b4e8815ac77a
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-15 (Thu, 15 May 2025)
Changed paths:
M llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
M llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
M llvm/test/MC/Mips/macro-rem.s
Log Message:
-----------
Mips,test: Fix check prefix
#140149
Commit: dc9171afc481f28865fc19ba7bc88c6596bb86e9
https://github.com/llvm/llvm-project/commit/dc9171afc481f28865fc19ba7bc88c6596bb86e9
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcibi.ll
Log Message:
-----------
[RISCV] Add isel patterns for generating Xqcibi branch instructions (#139872)
Add ISEL patterns for generating the Xqcibi branch immediate
instructions. Similar to #135771 adds new CondCodes for the various
branch instructions and uses them to return the appropriate instruction.
Commit: ca6398c79e43ea1289bfec8c623a55f47ed3f992
https://github.com/llvm/llvm-project/commit/ca6398c79e43ea1289bfec8c623a55f47ed3f992
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
A llvm/test/CodeGen/Mips/private-global-prefix.ll
Log Message:
-----------
[COFF][Mips] Set PrivateGlobalPrefix to .L (#140033)
When calling external functions which start with `L`, would generate
error: assembler label 'LeaveFoo' can not be undefined. This pr would
fix this issue.
Fix #134914.
Commit: 680b3b742da02972bc0b5298b6f472d2b95ca90a
https://github.com/llvm/llvm-project/commit/680b3b742da02972bc0b5298b6f472d2b95ca90a
Author: Iris Shi <0.0 at owo.li>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
Log Message:
-----------
[RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (#140003)
Followup of #139495 and #139508
Commit: 253b1c0177fc2f9bb9ada0340d4f391ab1123cb2
https://github.com/llvm/llvm-project/commit/253b1c0177fc2f9bb9ada0340d4f391ab1123cb2
Author: Qinkun Bao <qinkun at google.com>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M .github/new-prs-labeler.yml
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/Basic/Attr.td
A clang/include/clang/CIR/Dialect/OpenACC/CIROpenACCTypeInterfaces.h
A clang/include/clang/CIR/Dialect/OpenACC/RegisterOpenACCExtensions.h
M clang/include/clang/Sema/Overload.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/SanitizerSpecialCaseList.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenACC/CIROpenACCTypeInterfaces.cpp
A clang/lib/CIR/Dialect/OpenACC/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenACC/RegisterOpenACCExtensions.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/CIR/CodeGenOpenACC/data.c
M clang/test/CIR/CodeGenOpenACC/kernels.c
M clang/test/CIR/CodeGenOpenACC/parallel.c
M clang/test/CIR/CodeGenOpenACC/serial.c
M clang/test/CIR/CodeGenOpenACC/wait.c
M clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
A clang/test/CodeGenHLSL/RootSignature.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
A clang/test/CodeGenHLSL/convergence/global_array.hlsl
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
A clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/PointerLikeTest.cpp
M clang/unittests/CMakeLists.txt
M flang-rt/include/flang-rt/runtime/emit-encoded.h
M flang-rt/lib/runtime/edit-input.cpp
M flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenACC/acc-wait.f90
M llvm/docs/MLGO.rst
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
A llvm/include/llvm/ProfileData/DataAccessProf.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CGData/StableFunctionMapRecord.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVRange.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVReader.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVScope.cpp
M llvm/lib/Frontend/HLSL/HLSLRootSignature.cpp
M llvm/lib/MC/DXContainerRootSignature.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/ObjectYAML/DXContainerEmitter.cpp
M llvm/lib/ProfileData/CMakeLists.txt
A llvm/lib/ProfileData/DataAccessProf.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
A llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
R llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.path.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.5.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-vs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/use-native-low-precision-1.ll
A llvm/test/CodeGen/Mips/private-global-prefix.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
A llvm/test/CodeGen/RISCV/xqcibi.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
A llvm/test/MC/AsmParser/token.s
M llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
M llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
M llvm/test/MC/Mips/macro-rem.s
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/unittests/ProfileData/CMakeLists.txt
A llvm/unittests/ProfileData/DataAccessProfTest.cpp
A llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ProfileData/BUILD.gn
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Conversion/OpenACCToSCF/convert-openacc-to-scf.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[Sanitizer] Convert SpecialCaseList::Sections from StringMap to vector.
Created using spr 1.3.6
Compare: https://github.com/llvm/llvm-project/compare/716a389c97f7...253b1c0177fc
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