[all-commits] [llvm/llvm-project] 9a1bfc: [RISCV] Add SEXT_INREG patterns for Xqcibm ext ins...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a1bfc17d3acd33a5674cb442625f20495d5e5f5
      https://github.com/llvm/llvm-project/commit/9a1bfc17d3acd33a5674cb442625f20495d5e5f5
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-05-16 (Fri, 16 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcibm-extract.ll

  Log Message:
  -----------
  [RISCV] Add SEXT_INREG patterns for Xqcibm ext instruction (#140192)

Handle sign_extend_inreg from i1/i8/i16



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