[all-commits] [llvm/llvm-project] aa8a66: [MLIR][ArmSVE] Add initial lowering of `vector.con...

[Momchil Velikov via All-commits]

  Branch: refs/heads/users/momchil-velikov/vector-contract-i8mm
  Home:   https://github.com/llvm/llvm-project
  Commit: aa8a667f206874af3b26811ec04d58be12ad43de
      https://github.com/llvm/llvm-project/commit/aa8a667f206874af3b26811ec04d58be12ad43de
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M mlir/include/mlir/Conversion/Passes.td
    M mlir/include/mlir/Dialect/ArmSVE/Transforms/Transforms.h
    M mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
    M mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp
    M mlir/lib/Dialect/ArmSVE/Transforms/CMakeLists.txt
    A mlir/lib/Dialect/ArmSVE/Transforms/LowerContractionToSVEI8MMPattern.cpp
    A mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
    A mlir/test/Dialect/Vector/CPU/ArmSVE/vector-summla.mlir
    A mlir/test/Dialect/Vector/CPU/ArmSVE/vector-ummla.mlir
    A mlir/test/Dialect/Vector/CPU/ArmSVE/vector-usmmla.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-smmla-4x8x4.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-smmla-8x8x8-vs2.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-summla-4x8x4.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-ummla-4x8x4.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-usmmla-4x8x4.mlir

  Log Message:
  -----------
  [MLIR][ArmSVE] Add initial lowering of `vector.contract` to SVE `*MMLA` instructions


  Commit: f19fc7275c7708c1236ab49db66cd8086c72657d
      https://github.com/llvm/llvm-project/commit/f19fc7275c7708c1236ab49db66cd8086c72657d
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractionToSVEI8MMPattern.cpp

  Log Message:
  -----------
  [fixup] Misc changes

  -- come commenting
  -- replace enable_if with a staic assert
  -- return reasons for match failures


  Commit: c44b31e0dbcc6c8b9bd57de022639c5ee65b4523
      https://github.com/llvm/llvm-project/commit/c44b31e0dbcc6c8b9bd57de022639c5ee65b4523
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractionToSVEI8MMPattern.cpp
    M mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction-ummla-4x8x4.mlir

  Log Message:
  -----------
  [fixup] Handle implicit sign-extend of LHS and RHS


Compare: https://github.com/llvm/llvm-project/compare/32203d5b5573...c44b31e0dbcc

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