[all-commits] [llvm/llvm-project] 0bc399: [SelectionDAG] Add an ISD node for for get.active....

[Kerry McLaughlin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bc39937164f09823c906926d7eefd7a8bcb5161
      https://github.com/llvm/llvm-project/commit/0bc39937164f09823c906926d7eefd7a8bcb5161
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2025-05-15 (Thu, 15 May 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

  Log Message:
  -----------
  [SelectionDAG] Add an ISD node for for get.active.lane.mask (#139084)

For now expansion still happens in SelectionDAGBuilder when
GET_ACTIVE_LANE_MASK is not legal on the target.

This patch also includes changes in AArch64ISelLowering to replace
handling of the get.active.lane.mask intrinsic to use the ISD node.
Tablegen patterns are added which match to whilelo for scalable types.

A follow up change will add support for more types to be lowered to
GET_ACTIVE_LANE_MASK by allowing splitting of the node.



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