[all-commits] [llvm/llvm-project] e1b3af: [RISCV] Add isel patterns to use Zilsd for f64 loa...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e1b3af6dc4362c5281abf255c4078992ce64ad33
      https://github.com/llvm/llvm-project/commit/e1b3af6dc4362c5281abf255c4078992ce64ad33
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-14 (Wed, 14 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/test/CodeGen/RISCV/double-mem.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to use Zilsd for f64 load/store for Zdinx on RV32. (#139935)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications