[all-commits] [llvm/llvm-project] bf0655: [RISCV] Improve casting between i1 scalable vector...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf0655f2080248a59aa2b79f2579798b8158869c
      https://github.com/llvm/llvm-project/commit/bf0655f2080248a59aa2b79f2579798b8158869c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-14 (Wed, 14 May 2025)

  Changed paths:
    M clang/lib/CodeGen/CGCall.cpp
    M clang/lib/CodeGen/CGExprScalar.cpp
    M clang/test/CodeGen/RISCV/attr-riscv-rvv-vector-bits-less-8-call.c
    M clang/test/CodeGen/RISCV/attr-riscv-rvv-vector-bits-less-8-cast.c
    M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-bitcast-less-8.c
    M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-cast.c
    M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-codegen.c
    M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-globals.c
    M llvm/include/llvm/IR/DerivedTypes.h

  Log Message:
  -----------
  [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (#139190)

For i1 vectors, we used an i8 fixed vector as the storage type.

If the known minimum number of elements of the scalable vector type is
less than 8, we were doing the cast through memory. This used a load or
store from a fixed vector alloca. If  is less than 8, DataLayout
indicates that the load/store reads/writes vscale bytes even if vscale
is known and vscale*X is less than or equal to 8. This means the load or
store is outside the bounds of the fixed size alloca as far as
DataLayout is concerned leading to undefined behavior.

This patch avoids this by widening the i1 scalable vector type with zero
elements until it is divisible by 8. This allows it be bitcasted to/from
an i8 scalable vector. We then insert or extract the i8 fixed vector
into this type.

Hopefully this enables #130973 to be accepted.



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