[all-commits] [llvm/llvm-project] bbc522: [DAGCombiner] Fold pattern for srl-shl-zext (#138290)

[Alexander Peskov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbc5221c95343d8d6869dce83d6fcf183767bd9f
      https://github.com/llvm/llvm-project/commit/bbc5221c95343d8d6869dce83d6fcf183767bd9f
  Author: Alexander Peskov <apeskov at nvidia.com>
  Date:   2025-05-14 (Wed, 14 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/NVPTX/shift-opt.ll

  Log Message:
  -----------
  [DAGCombiner] Fold pattern for srl-shl-zext (#138290)

Fold `(srl (lop x, (shl (zext y), c1)), c1) -> (lop (srl x, c1), (zext y))` where c1 <= leadingzeros(zext(y)).

This is equivalent of existing fold chain `(srl (shl (zext y), c1), c1) -> (and (zext y), mask) -> (zext y)`, but logical op in the middle prevents it from combining.

Profit : Allow to reduce the number of instructions.

---------

Signed-off-by: Alexander Peskov <apeskov at nvidia.com>



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