[all-commits] [llvm/llvm-project] af6261: [DAG] visitINSERT_VECTOR_ELT - convert to or mask ...

[AZero13 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af6261b50bc2e2dce73ed0f24f6175d460be3b1c
      https://github.com/llvm/llvm-project/commit/af6261b50bc2e2dce73ed0f24f6175d460be3b1c
  Author: AZero13 <gfunni234 at gmail.com>
  Date:   2025-05-13 (Tue, 13 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/X86/avx-cvt-3.ll
    M llvm/test/CodeGen/X86/insertelement-ones.ll

  Log Message:
  -----------
  [DAG] visitINSERT_VECTOR_ELT - convert to or mask if all insertions are -1 (#138213)

We did this for 0 and and, but we can do this with or and -1.

Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>



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