[all-commits] [llvm/llvm-project] 9570bf: [TableGen][MacroFusion] Predicate if the first ins...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9570bf978d77aa53fffb50c60388da8f1bd71e4c
      https://github.com/llvm/llvm-project/commit/9570bf978d77aa53fffb50c60388da8f1bd71e4c
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-05-13 (Tue, 13 May 2025)

  Changed paths:
    M llvm/include/llvm/Target/TargetMacroFusion.td
    M llvm/test/TableGen/MacroFusion.td
    M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp

  Log Message:
  -----------
  [TableGen][MacroFusion] Predicate if the first inst has the same register (#137778)

We rename `SameReg` to `SecondInstHasSameReg ` and add
`FirstInstHasSameReg `
which has the logic but applies to the first instruction.

We have some cases that require the first instruction has the same
input/output register.



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