[all-commits] [llvm/llvm-project] 80547c: [X86][APX] Fix issues of suppressing APX for reloc...

[Feng Zou via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80547cd7051316ac7b1a5c156c28b4b9988a6168
      https://github.com/llvm/llvm-project/commit/80547cd7051316ac7b1a5c156c28b4b9988a6168
  Author: Feng Zou <feng.zou at intel.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp
    A llvm/test/CodeGen/X86/apx/reloc-opt.ll
    M llvm/test/CodeGen/X86/apx/reloc.mir

  Log Message:
  -----------
  [X86][APX] Fix issues of suppressing APX for relocation (#139285)

1. There is ADD64rm_ND instruction emitted with GOTPCREL relocation.
Handled it in "Suppress APX for relocation" pass and transformed it to
ADD64rm with register operand in non-rex2 register class. The relocation
type R_X86_64_CODE_6_GOTPCRELX will be added later for APX enabled with
relocation.
2. The register class for operands in instruction with relocation is
updated to non-rex2 one in "Suppress APX for relocation" pass, but it
may be updated/recomputed to larger register class (like
GR64_NOREX2RegClass to GR64RegClass). Fixed by not updating the register
class if it's non-rex2 register class and APX support for relocation is
disabled.
3. After "Suppress APX for relocation" pass, the instruction with
relocation may be folded with add NDD instruction to a add NDD
instruction with relocation. The later will be emitted to instruction
with APX relocation type which breaks backward compatibility. Fixed by
not folding instruction with GOTPCREL relocation with NDD instruction.
4. If the register in operand 0 of instruction with relocation is used
in the PHI instruction, it may be replaced with operand 0 of PHI
instruction (maybe EGPR) after PHI elimination and Machine Copy
Propagation pass. Fixed by suppressing EGPR in operand 0 of PHI
instruction to avoid APX relocation types emitted.



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