[all-commits] [llvm/llvm-project] 3c1d3a: [GlobalISel] Add G_SHUFFLE_VECTOR computeKnownBits

[David Green via All-commits]

  Branch: refs/heads/users/davemgreen/gh-gi-ashr
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c1d3a6a78d8e397584f07b660c034017f8d9022
      https://github.com/llvm/llvm-project/commit/3c1d3a6a78d8e397584f07b660c034017f8d9022
  Author: David Green <david.green at arm.com>
  Date:   2025-05-11 (Sun, 11 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll

  Log Message:
  -----------
  [GlobalISel] Add G_SHUFFLE_VECTOR computeKnownBits

The code is taken from SelectionDAG::computeKnownBits.


  Commit: ba2e853f610a46f5d3779b4fd61a44e46150652f
      https://github.com/llvm/llvm-project/commit/ba2e853f610a46f5d3779b4fd61a44e46150652f
  Author: David Green <david.green at arm.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll

  Log Message:
  -----------
  [GlobalISel] Add computeNumSignBits for ASHR


Compare: https://github.com/llvm/llvm-project/compare/3c1d3a6a78d8%5E...ba2e853f610a

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