[all-commits] [llvm/llvm-project] ef40ae: [SelectionDAG] Fix incorrect fold condition in fol...

[Rux124 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ef40ae4f4e273828e81de08a8b5ab71ac3f59c79
      https://github.com/llvm/llvm-project/commit/ef40ae4f4e273828e81de08a8b5ab71ac3f59c79
  Author: Rux124 <143302514+Ruhung at users.noreply.github.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/setcc-fsh.ll

  Log Message:
  -----------
  [SelectionDAG] Fix incorrect fold condition in foldSetCCWithFunnelShift. (#137637)

Proposed by
[2ed1598](https://github.com/llvm/llvm-project/commit/2ed15984b49a1af87be37ec8bd6ee3ab7f724767):

`fshl X, (or X, Y), C ==/!= 0 --> or (srl Y, BW-C), X ==/!= 0`

This transformation is valid when (C%Bitwidth) != 0 , as verified by
[Alive2](https://alive2.llvm.org/ce/z/TQYM-m).

Fixes #136746



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