[all-commits] [llvm/llvm-project] 5b9175: [RISCV][Peephole] Checking regclass compatibility ...

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b91756c0ca7ef4d75c33c2617bfd0f9719907dc
      https://github.com/llvm/llvm-project/commit/5b91756c0ca7ef4d75c33c2617bfd0f9719907dc
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

  Log Message:
  -----------
  [RISCV][Peephole] Checking regclass compatibility in VMV (#138844)

Without checking the regclass compatibility, this pass may generate bad
machine code.

```
*** Bad machine code: Illegal virtual register for instruction ***
- function:    main
- basic block: %bb.0 entry (0x9209848)
- instruction: %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %0:vr(tied-def 0), %0:vr, %0:vr, %4:vmv0, 0, 5, 0
- operand 1:   %0:vr(tied-def 0)
Expected a VRNoV0 register, but got a VR register
```

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>



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