[all-commits] [llvm/llvm-project] aeb5a5: [RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicat...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aeb5a58d24f02f09abd35bfde5a294b7d2c8ffdc
      https://github.com/llvm/llvm-project/commit/aeb5a58d24f02f09abd35bfde5a294b7d2c8ffdc
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)

`VLDSX0Pred` is used for scheduling vector zero-stride load/store.



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