[all-commits] [llvm/llvm-project] a788a1: [RISCV] Implement codegen for XAndesPerf lea instr...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a788a1abd9c881aa113f5932d100e1a2e3898e14
      https://github.com/llvm/llvm-project/commit/a788a1abd9c881aa113f5932d100e1a2e3898e14
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-05-12 (Mon, 12 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zba.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Implement codegen for XAndesPerf lea instructions (#137925)

This patch add the patterns for generating XAndesPerf lea instructions.

The operation of LEA family instructions is:

  rd = rs1 + rs2 * (the number of bytes)

The variants with *.ze suffix are RV64 only and its operation is:

  rd = rs1 + ZE32(rs2[31:0]) * (the number of bytes)



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