[all-commits] [llvm/llvm-project] f615a5: pre-commit test

[Iris Shi via All-commits]

  Branch: refs/heads/users/el-ev/fold-masked-merge
  Home:   https://github.com/llvm/llvm-project
  Commit: f615a5caec2096c713c32a3316b447ddf4cd8788
      https://github.com/llvm/llvm-project/commit/f615a5caec2096c713c32a3316b447ddf4cd8788
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-05-11 (Sun, 11 May 2025)

  Changed paths:
    A llvm/test/CodeGen/RISCV/fold-masked-merge.ll
    A llvm/test/CodeGen/SystemZ/fold-masked-merge.ll

  Log Message:
  -----------
  pre-commit test

pre-commit systemz test


  Commit: 25e5974a6b9a68e30e1416eee6f54fb42270d4e2
      https://github.com/llvm/llvm-project/commit/25e5974a6b9a68e30e1416eee6f54fb42270d4e2
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-05-11 (Sun, 11 May 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/RISCV/fold-masked-merge.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
    M llvm/test/CodeGen/WebAssembly/simd-arith.ll
    M llvm/test/CodeGen/X86/bitselect.ll
    M llvm/test/CodeGen/X86/fold-masked-merge.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td

  Log Message:
  -----------
  [SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` available for all targets

update affected tests

formatting

pre-commit systemz test

fix systemz hasandnot

fix random tablegen test

move hasAndNot

Update llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td


Compare: https://github.com/llvm/llvm-project/compare/9cc2038f8460...25e5974a6b9a

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