[all-commits] [llvm/llvm-project] 3c8c76: [𝘀𝗽𝗿] initial version

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/spr/selectiondagbuilder-use-address-width-when-lowering-ptrtoaddr
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c8c76e13841a8f9b8c5036609c6112e69ad4ccd
      https://github.com/llvm/llvm-project/commit/3c8c76e13841a8f9b8c5036609c6112e69ad4ccd
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2025-05-10 (Sat, 10 May 2025)

  Changed paths:
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/test/CodeGen/target-data.c
    M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
    M llvm/docs/LangRef.rst
    M llvm/include/llvm-c/Core.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
    M llvm/include/llvm/IR/DataLayout.h
    M llvm/include/llvm/IR/InstVisitor.h
    M llvm/include/llvm/IR/Instruction.def
    M llvm/include/llvm/IR/Instructions.h
    M llvm/include/llvm/SandboxIR/Instruction.h
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/Instruction.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/SandboxIR/Context.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/test/Analysis/StackSafetyAnalysis/extend-ptr.ll
    A llvm/test/Assembler/ptrtoaddr-const.ll
    A llvm/test/Assembler/ptrtoaddr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
    M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
    M llvm/test/CodeGen/AMDGPU/ptrmask.ll
    A llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr-p8.ll
    A llvm/test/CodeGen/X86/GlobalISel/ptrtoaddr.ll
    A llvm/test/CodeGen/X86/ptrtoaddr.ll
    M llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll
    M llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll
    M llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
    M llvm/test/Transforms/IRNormalizer/regression-convergence-tokens.ll
    M llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
    M llvm/test/Transforms/IRNormalizer/reordering-basic.ll
    M llvm/test/Transforms/IRNormalizer/reordering.ll
    M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
    M llvm/test/Transforms/InferAddressSpaces/X86/noop-ptrint-pair.ll
    M llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
    M llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
    M llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
    M llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
    M llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
    M llvm/test/Transforms/OpenMP/values_in_offload_arrays.alloca.ll
    M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
    M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
    M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
    M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
    M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
    M mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir
    M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
    M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
    M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
    M mlir/test/Target/LLVMIR/omptarget-private-llvm.mlir
    M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
    M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
    M mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir
    M mlir/test/Target/LLVMIR/omptarget-wsloop.mlir

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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