[all-commits] [llvm/llvm-project] 70a6d6: [RISCV][MC] Add support for Q extension

[Iris Shi via All-commits]

  Branch: refs/heads/users/el-ev/riscv-q-ext
  Home:   https://github.com/llvm/llvm-project
  Commit: 70a6d632c96de6564eea070d526bbbeaa8df3f08
      https://github.com/llvm/llvm-project/commit/70a6d632c96de6564eea070d526bbbeaa8df3f08
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-05-10 (Sat, 10 May 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
    M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
    M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
    M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/MC/RISCV/rv32q-invalid.s
    A llvm/test/MC/RISCV/rv64q-invalid.s
    A llvm/test/MC/RISCV/rv64q-valid.s
    A llvm/test/MC/RISCV/rvq-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Add support for Q extension



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