[all-commits] [llvm/llvm-project] 764614: [MemProf] Restructure the pruning of unneeded NotC...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu May 8 14:43:20 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/nfcubsan_minimal-clang-format-a-file
Home: https://github.com/llvm/llvm-project
Commit: 764614e6355e214c6b64c715d105007b1a4b97fd
https://github.com/llvm/llvm-project/commit/764614e6355e214c6b64c715d105007b1a4b97fd
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/test/Transforms/PGOProfile/memprof.ll
Log Message:
-----------
[MemProf] Restructure the pruning of unneeded NotCold contexts (#138792)
This change is mostly NFC, other than the addition of a new message
printed when contexts are pruned when -memprof-report-hinted-sizes is
enabled.
To prepare for a follow on change, adjust the way we determine which
NotCold contexts can be pruned (because they overlap with longer NotCold
contexts), and change the way we perform this pruning.
Instead of determining the points at which we need to keep NotCold
contexts during the building of the trie, we now determine this on the
fly as the MIB metadata nodes are recursively built. This simplifies a
follow on change that performs additional pruning of some NotCold
contexts, and which can affect which others need to be kept as the
longest overlapping NotCold contexts.
Commit: 7245e21e896a39fbbbbe38e800791411ebde4011
https://github.com/llvm/llvm-project/commit/7245e21e896a39fbbbbe38e800791411ebde4011
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclOpenACC.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Sema/ParsedTemplate.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclObjC.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/Type.cpp
M clang/tools/libclang/CXIndexDataConsumer.cpp
M lldb/source/Utility/Checksum.cpp
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/DebugInfo/MSF/MSFBuilder.cpp
M llvm/lib/IR/AttributeImpl.h
M llvm/lib/ObjectYAML/MinidumpEmitter.cpp
M llvm/lib/Support/FoldingSet.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/unittests/Support/TrailingObjectsTest.cpp
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/Support/StorageUniquer.h
M mlir/lib/Dialect/Affine/Analysis/NestedMatcher.cpp
M mlir/lib/IR/AffineMapDetail.h
M mlir/lib/IR/Location.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/lib/Tools/PDLL/AST/Nodes.cpp
Log Message:
-----------
[NFC][Support] Add llvm::uninitialized_copy (#138174)
Add `llvm::uninitialized_copy` that accepts a range instead of start/end
iterator for the source of the copy.
Commit: 482e9b06d84ef230f8fe2d0b25ae91d38896e697
https://github.com/llvm/llvm-project/commit/482e9b06d84ef230f8fe2d0b25ae91d38896e697
Author: Lang Hames <lhames at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/ELF_i386.cpp
Log Message:
-----------
[JITLink][i386] Drop EdgeKind_i386 qualification when using enum values.
We don't need to explicitly qualify these values.
Commit: e0e3d05a2e048c95b6eaa4b08f41b4c7ac66a023
https://github.com/llvm/llvm-project/commit/e0e3d05a2e048c95b6eaa4b08f41b4c7ac66a023
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[RISCV] Fix the link to the XAndesPerf specification. NFC (#138804)
We need to use 2 underscores after the URL like the other specification
links.
Commit: c7f350f1428df14e3114977b830ab4dcd3008983
https://github.com/llvm/llvm-project/commit/c7f350f1428df14e3114977b830ab4dcd3008983
Author: Lang Hames <lhames at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/i386.h
Log Message:
-----------
[JITLink][i386] Remove more unnecessary enum value qualifications.
Commit: b972164f38133fbc878275f4ae324908ae14d750
https://github.com/llvm/llvm-project/commit/b972164f38133fbc878275f4ae324908ae14d750
Author: Lang Hames <lhames at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
R llvm/include/llvm/ExecutionEngine/JITLink/ELF_i386.h
A llvm/include/llvm/ExecutionEngine/JITLink/ELF_x86.h
R llvm/include/llvm/ExecutionEngine/JITLink/i386.h
A llvm/include/llvm/ExecutionEngine/JITLink/x86.h
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
R llvm/lib/ExecutionEngine/JITLink/ELF_i386.cpp
A llvm/lib/ExecutionEngine/JITLink/ELF_x86.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
R llvm/lib/ExecutionEngine/JITLink/i386.cpp
A llvm/lib/ExecutionEngine/JITLink/x86.cpp
R llvm/test/ExecutionEngine/JITLink/i386/ELF_external_to_absolute_conversion.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_absolute_relocations_16.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_absolute_relocations_32.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_minimal.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_pc_relative_relocations_32.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_small_pic_relocations_got.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_small_pic_relocations_plt.s
R llvm/test/ExecutionEngine/JITLink/i386/lit.local.cfg
A llvm/test/ExecutionEngine/JITLink/x86/ELF_external_to_absolute_conversion.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_absolute_relocations_16.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_absolute_relocations_32.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_minimal.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_pc_relative_relocations_32.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_small_pic_relocations_got.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_small_pic_relocations_plt.s
A llvm/test/ExecutionEngine/JITLink/x86/lit.local.cfg
Log Message:
-----------
[JITLink] Rename 'i386' namespace and files to 'x86'.
When building on i386, both clang and gcc define a builtin 'i386' macro (see
discussion in https://github.com/llvm/llvm-project/pull/137063). This causes
build errors in the JITLink/i386 backend when attempting to build LLVM on i386.
This commit renames the 'i386' backend (namespaces, APIs and files) to 'x86' to
avoid this issue.
Commit: c16297cd3f0ed9d036e9cf16fb6885aa3c72d5d3
https://github.com/llvm/llvm-project/commit/c16297cd3f0ed9d036e9cf16fb6885aa3c72d5d3
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
A clang/test/SemaCUDA/overloaded-builtin.cu
Log Message:
-----------
[CUDA][HIP] Fix host/device attribute of builtin (#138162)
When a builtin function is passed a pointer with a different
address space, clang creates an overloaded
builtin function but does not copy the host/device attribute. This
causes
error when the builtin is called by device functions
since CUDA/HIP relies on the host/device attribute to treat
a builtin function as callable on both host and device
sides.
Fixed by copying the host/device attribute of the original
builtin function to the created overloaded builtin function.
Commit: 57bc9f000600773a3e0a272e1154df87581c7b57
https://github.com/llvm/llvm-project/commit/57bc9f000600773a3e0a272e1154df87581c7b57
Author: Lang Hames <lhames at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/x86.cpp
M llvm/unittests/ExecutionEngine/JITLink/StubsTests.cpp
Log Message:
-----------
[JITLink][x86] Update StubsTest unit test for rename in b972164f381.
Commit: eebb50afaf27961b21847950179febdd20a98866
https://github.com/llvm/llvm-project/commit/eebb50afaf27961b21847950179febdd20a98866
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
Log Message:
-----------
[gn build] Port b972164f3813
Commit: dc28f9d087324f77db81e7192648a17ebf036125
https://github.com/llvm/llvm-project/commit/dc28f9d087324f77db81e7192648a17ebf036125
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
Log Message:
-----------
[clang][ExprConstant] Bail out on invalid lambda capture inits (#138832)
Fixes https://github.com/llvm/llvm-project/issues/138824
Commit: 92d3029fa4a9c6ce21c50590e57ae834ae3db3bc
https://github.com/llvm/llvm-project/commit/92d3029fa4a9c6ce21c50590e57ae834ae3db3bc
Author: cmtice <cmtice at google.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
A lldb/test/API/lang/cpp/type_lookup_anon_struct/Makefile
A lldb/test/API/lang/cpp/type_lookup_anon_struct/TestCppTypeLookupAnonStruct.py
A lldb/test/API/lang/cpp/type_lookup_anon_struct/main.cpp
Log Message:
-----------
[LLDB] Fix GetIndexOfChildMemberWithName to handle anonymous structs. (#138487)
When handling anonymous structs, GetIndexOfChildMemberWithName needs to
add the number of non-empty base classes to the child index, to get the
actual correct index. It was not doing so. This fixes that.
Commit: efce7a169e58ec8b27d266ec4dfb851f85a7c6c2
https://github.com/llvm/llvm-project/commit/efce7a169e58ec8b27d266ec4dfb851f85a7c6c2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attachByPortNum.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/commands/TestDAP_commands.py
M lldb/test/API/tools/lldb-dap/disassemble/TestDAP_disassemble.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
Log Message:
-----------
[lldb-dap] Re-enable the lldb-dap tests (#138791)
Re-enable the lldb-dap tests. We've spent the last week improving the
reliability of the test suite and the tests now pass reliably on macOS
and Linux at desk. Let's see how things fare on the bots.
Commit: efd805ed5591b557d66c95c1ca11701ef7bc897d
https://github.com/llvm/llvm-project/commit/efd805ed5591b557d66c95c1ca11701ef7bc897d
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
A llvm/test/MC/AsmParser/quoted.s
Log Message:
-----------
MC: Test quoted label
Commit: 7348d7eccbc452ed1fd9bc219c796f1214a3cc84
https://github.com/llvm/llvm-project/commit/7348d7eccbc452ed1fd9bc219c796f1214a3cc84
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[MemProf] Avoid assertion checking loop under NDEBUG (NFC) (#138985)
Guard a loop that only exists to do assertion checking of stack ids on
memprof metadata so that it isn't compiled and executed under NDEBUG.
This is similar to how callsite metadata stack id verification is
guarded further below.
Commit: 20d6375796073f6a0f0ea6abe05ce454a3d617ff
https://github.com/llvm/llvm-project/commit/20d6375796073f6a0f0ea6abe05ce454a3d617ff
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/CodeGen/ms_abi.c
M clang/test/CodeGen/sysv_abi.c
M clang/test/Sema/callingconv-ms_abi.c
M clang/test/Sema/varargs-win64.c
Log Message:
-----------
[clang] Handle CC attrs for UEFI (#138935)
UEFI's default ABI is MS ABI. Handle the calling convention attributes
accordingly.
Commit: 98d26b8f67e6abdac24591138f07dc34e7f0e36e
https://github.com/llvm/llvm-project/commit/98d26b8f67e6abdac24591138f07dc34e7f0e36e
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
Log Message:
-----------
[libc][bazel] Re-enable memcpy prefetching on x86. (#138945)
It was re-enabled downstream after further performance analysis, so we
can revert c65ed964657c93d51f3e05de9e0609419768a143, effectively
re-landing the change.
Commit: 28521368d74a7ea264ce7cf2f51e48f92c4f53a5
https://github.com/llvm/llvm-project/commit/28521368d74a7ea264ce7cf2f51e48f92c4f53a5
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 6babd63a4bbc094bee4ef8e75f95dccd32325c15 (#139026)
Commit: 215dbcb2bc5c1b1bc8775db2a7c22f67f3949fd7
https://github.com/llvm/llvm-project/commit/215dbcb2bc5c1b1bc8775db2a7c22f67f3949fd7
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Enable header processing for C++ builds. (#138934)
This would only work for projects that explicitly enable "parse_headers"
feature (or for builds that specify this on command-line) - right now
there are none, so this change shouldn't affect most builds. When
"parse_headers" is enabled though, it would catch problems of
incorrect/missing includes in header-only cc_libraries.
See https://bazel.build/docs/bazel-and-cpp#toolchain-features on why
this option is a best practice for C++ projects.
Commit: ab2e7aa5179ab7ba83fa7f731df63a1adbf7612c
https://github.com/llvm/llvm-project/commit/ab2e7aa5179ab7ba83fa7f731df63a1adbf7612c
Author: dyung <douglas.yung at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/attr-trivial-abi.cpp
M clang/test/SemaCXX/ptrauth-triviality.cpp
M clang/test/SemaCXX/type-traits-nonobject.cpp
Log Message:
-----------
Revert "[Clang] Deprecate `__is_trivially_relocatable`" (#139027)
Reverts llvm/llvm-project#138835
This is causing a test failure on a bot:
https://lab.llvm.org/buildbot/#/builders/144/builds/24541
Commit: fa09d031d3f3a5018e626938ef76b7072a298dfd
https://github.com/llvm/llvm-project/commit/fa09d031d3f3a5018e626938ef76b7072a298dfd
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate ObjC `* __autoreleasing *` (#138799)
Fix #138484
Commit: 26572bad95f816a979ce70b4e1335c8438a96df2
https://github.com/llvm/llvm-project/commit/26572bad95f816a979ce70b4e1335c8438a96df2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp
M clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl
Log Message:
-----------
clang/OpenCL: Add baseline test showing broken codegen (#138862)
Commit: 5df01abe191ff4f848566e239798a2b4d26e1cf4
https://github.com/llvm/llvm-project/commit/5df01abe191ff4f848566e239798a2b4d26e1cf4
Author: Filip Milosevic <54005272+MightyFilipns at users.noreply.github.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add SpaceAfterOperatorKeyword option (#137610)
Add SpaceAfterOperatorKeyword option to clang-format
Commit: a11d86461e7d7d9bce3d04a39ded1cad394239ca
https://github.com/llvm/llvm-project/commit/a11d86461e7d7d9bce3d04a39ded1cad394239ca
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
M clang/test/CodeGenOpenCL/blocks.cl
M clang/test/CodeGenOpenCL/builtins-alloca.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/implicit-addrspacecast-function-parameter.cl
M clang/test/Index/pipe-size.cl
Log Message:
-----------
clang: Fix broken implicit cast to generic address space (#138863)
This fixes emitting undefined behavior where a 64-bit generic
pointer is written to a 32-bit slot allocated for a private pointer.
This can be seen in test/CodeGenOpenCL/amdgcn-automatic-variable.cl's
wrong_pointer_alloca.
Commit: 334c1abdb0bee488477f810ebf4cc1d41c31e653
https://github.com/llvm/llvm-project/commit/334c1abdb0bee488477f810ebf4cc1d41c31e653
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A llvm/test/CodeGen/X86/codegen-no-uselist-constantdata.ll
A llvm/test/Transforms/CorrelatedValuePropagation/no-uselist-constantdata-regression.ll
Log Message:
-----------
Add regression tests from ConstantData uselist removal (#138960)
Add some examples of failures after 87f312aad6ede636cd2de5d18f3058bf2caf5651
Commit: 9383fb23e18bb983d0024fb956a0a724ef9eb03d
https://github.com/llvm/llvm-project/commit/9383fb23e18bb983d0024fb956a0a724ef9eb03d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Use.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/AssumeBundleQueries.cpp
M llvm/lib/Analysis/TypeMetadataUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Use.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/test/Analysis/MemorySSA/nondeterminism.ll
A llvm/test/tools/llvm-diff/uselistorder-issue58629-gv.ll
M llvm/test/tools/llvm-diff/uselistorder-issue58629.ll
M llvm/test/tools/llvm-reduce/bitcode-uselistorder.ll
M llvm/test/tools/llvm-reduce/uselistorder-invalid-ir-output.ll
M llvm/tools/verify-uselistorder/verify-uselistorder.cpp
M polly/lib/Support/ScopHelper.cpp
Log Message:
-----------
Reapply "IR: Remove uselist for constantdata (#137313)" (#138961)
Reapply "IR: Remove uselist for constantdata (#137313)"
This reverts commit 5936c02c8b9c6d1476f7830517781ce8b6e26e75.
Fix checking uselists of constants in assume bundle queries
Commit: 4d60c6d9b2c863d773aac9b59af8780e5ba23fcd
https://github.com/llvm/llvm-project/commit/4d60c6d9b2c863d773aac9b59af8780e5ba23fcd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Use.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Value.cpp
M llvm/unittests/IR/ConstantsTest.cpp
Log Message:
-----------
Reapply "IR: Remove reference counts from ConstantData (#137314)" (#138962)
This reverts commit 0274232b87177779e5c985eca06df22bf140f6cb.
Commit: 87db0943e4d07640e4df3206045826c0688ed3b9
https://github.com/llvm/llvm-project/commit/87db0943e4d07640e4df3206045826c0688ed3b9
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/test/MC/AsmParser/quoted.s
M llvm/test/MC/COFF/safeseh.s
M llvm/test/MC/ELF/symbol-names.s
Log Message:
-----------
MC: Support quoted symbol names
gas has supported " quoted symbols since 2015:
https://sourceware.org/pipermail/binutils/2015-August/090003.html
We don't handle \\ or \" , leading to clang -c --save-temps vs clang -c
difference for the following C code:
```
int x asm("a\"\\b");
```
Fix #138390
MC/COFF/safeseh.h looks incorrect. \01 in `.safeseh "\01foo"` is not a
correct escape sequence. Change it to \\
Pull Request: https://github.com/llvm/llvm-project/pull/138817
Commit: df4eac2f8b6d32772953d3d8063568fe4c0314c1
https://github.com/llvm/llvm-project/commit/df4eac2f8b6d32772953d3d8063568fe4c0314c1
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-05-07 (Wed, 07 May 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
Log Message:
-----------
[lldb-dap] Temporarily disable the breakpoint tests
At least one of these tests is failing every run on GreenDragon:
https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/as-lldb-cmake/
Commit: fc8484f0e383cc5cf31d67ad3e762705955ea1ea
https://github.com/llvm/llvm-project/commit/fc8484f0e383cc5cf31d67ad3e762705955ea1ea
Author: Matthias Springer <me at m-sp.org>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Rename `MaterializationCallbackFn` (#138814)
There are two kind of materialization callbacks: one for target
materializations and one for source materializations. The callback type
for target materializations is `TargetMaterializationCallbackFn`. This
commit renames the one for source materializations from
`MaterializationCallbackFn` to `SourceMaterializationCallbackFn`, for
consistency.
There used to be a single callback type for both kind of
materializations, but the materialization function signatures have
changed over time.
Also clean up a few places in the documentation that still referred to
argument materializations.
Commit: e7bf75043701119f8aeecff4c203cbcf2266fa62
https://github.com/llvm/llvm-project/commit/e7bf75043701119f8aeecff4c203cbcf2266fa62
Author: fengfeng <153487255+fengfeng09 at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
A llvm/test/Transforms/InstCombine/or-or-combine.ll
Log Message:
-----------
[InstCombine] Pass disjoint in or combine (#138800)
Proof: https://alive2.llvm.org/ce/z/wtTm5V
https://alive2.llvm.org/ce/z/WC7Ai2
---------
Signed-off-by: feng.feng <feng.feng at iluvatar.com>
Commit: c099caa292cb93b441b1082a9ea59265721bce13
https://github.com/llvm/llvm-project/commit/c099caa292cb93b441b1082a9ea59265721bce13
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
Log Message:
-----------
[MLIR][TOSA-Linalg] Fix rescale lowering for unsigned input zp (#138780)
Lowering of tosa.rescale to Linalg unconditionally sign-extend the input
zero-point value, even when unsigned_input is true. This commit refactor
zeropoint handling to share the same logic between input and output
zeropoint.
Commit: 09984be7d9c8b4ccb8fc27b0533c049f384a898f
https://github.com/llvm/llvm-project/commit/09984be7d9c8b4ccb8fc27b0533c049f384a898f
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
R llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll
M llvm/test/CodeGen/X86/asm-modifier-macho.ll
M llvm/test/CodeGen/X86/asm-modifier.ll
R llvm/test/CodeGen/X86/pr19752.ll
Log Message:
-----------
X86,test: Improve asm modifier tests
Commit: e18f248956b317f06f7822920c72d7a2eebcd267
https://github.com/llvm/llvm-project/commit/e18f248956b317f06f7822920c72d7a2eebcd267
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
Log Message:
-----------
[lldb][test] Disable flaky test_qThreadInfo_matches_qC_attach test on AArch64 Linux (#138940)
See #138085 for details.
https://lab.llvm.org/buildbot/#/builders/59/builds/16937
https://lab.llvm.org/buildbot/#/builders/59/builds/17224
Commit: 19174126cfe9f7e392104bd0bc56ca8ffb674115
https://github.com/llvm/llvm-project/commit/19174126cfe9f7e392104bd0bc56ca8ffb674115
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Simplify buildTree() legality checks (NFC) (#138833)
This NFC aims to simplify the interfaces used in `buildTree()` to make
it easier to understand where decisions for legality are made.
In particular, there is now a single point of definition for legality
decisions. This makes it clear where all those decisions are made.
Previously, multiple variables with a large scope were passed by
reference.
Commit: d307c774d0dd5062199f6d97b2184cb76e157542
https://github.com/llvm/llvm-project/commit/d307c774d0dd5062199f6d97b2184cb76e157542
Author: Fangrui Song <i at maskray.me>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A llvm/test/CodeGen/X86/asm-modifier-pic.ll
M llvm/test/CodeGen/X86/asm-modifier.ll
Log Message:
-----------
X86: Add asm modifier tests for 64-bit PIC
Commit: 01761a73e4d74bf1f84537b00fd89d7e75b71f5b
https://github.com/llvm/llvm-project/commit/01761a73e4d74bf1f84537b00fd89d7e75b71f5b
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
Log Message:
-----------
[AMDGPU] Add missing intrinsic declaration to intrinsics.ll. NFC. (#138954)
Commit: 5b8664fcb253fbd9eb0e83db3c1c0e19dd2499ef
https://github.com/llvm/llvm-project/commit/5b8664fcb253fbd9eb0e83db3c1c0e19dd2499ef
Author: haonan <haonan.yang at intel.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
A llvm/test/Transforms/InstCombine/fold-phi-arg-gep-to-phi-negative.ll
Log Message:
-----------
[InstCombine][foldPHIArgGEPIntoPHI] Early return for const vector index for gep inst (#138661)
Commit: 2b140932880db4d7a220b1b76eff4eec15066c58
https://github.com/llvm/llvm-project/commit/2b140932880db4d7a220b1b76eff4eec15066c58
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
Log Message:
-----------
[CodeGen] Parse nusw flag (#138856)
Fixes #127781
Commit: 2668167e2cf935528f7d93cb3b12a651a29e52f6
https://github.com/llvm/llvm-project/commit/2668167e2cf935528f7d93cb3b12a651a29e52f6
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
Log Message:
-----------
[lldb] Disable some lldb-dap tests on Windows
Since https://github.com/llvm/llvm-project/pull/138981 / https://github.com/llvm/llvm-project/commit/aeeb9a3c09f40f42a1e8e5e3c8dbde3b260744bd
were landed and tests re-enabled, these tests have been failing
on our Windows on Arm bot:
https://lab.llvm.org/buildbot/#/builders/141/builds/8523
********************
Unresolved Tests (1):
lldb-api :: tools/lldb-dap/send-event/TestDAP_sendEvent.py
********************
Failed Tests (2):
lldb-api :: tools/lldb-dap/launch/TestDAP_launch.py
lldb-api :: tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
Commit: 2a32d738bb213a8a1e814b65beb61e39b7c66834
https://github.com/llvm/llvm-project/commit/2a32d738bb213a8a1e814b65beb61e39b7c66834
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/sections-predetermined-private.f90
Log Message:
-----------
[flang][OpenMP] fix predetermined privatization inside section (#138159)
This now produces code equivalent to if there was an explicit private
clause on the SECTIONS construct.
The problem was that each SECTION construct got its own DSP, which tried
to privatize the same symbol for that SECTION. Privatization for
SECTION(S) happens on the outer SECTION construct and so the outer
construct's DSP should be shared.
Fixes #135108
Commit: 18f89283ebac87a153708b8fe00056f96b83022a
https://github.com/llvm/llvm-project/commit/18f89283ebac87a153708b8fe00056f96b83022a
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Fix mul folder conformance to the spec (#137601)
Change the folder for mul with a shift such that the rounding happens
correctly according to the spec
pesudo-code.
Fixes:
https://discourse.llvm.org/t/tosa-mul-i32-shift-incorrect-result/86040
Partial cherry-pick from:
https://github.com/llvm/llvm-project/pull/128059
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: fc2ec06ccab498447914c076f1e7b4326dc321c2
https://github.com/llvm/llvm-project/commit/fc2ec06ccab498447914c076f1e7b4326dc321c2
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/DebugInfo/KeyInstructions/X86/parse.mir
Log Message:
-----------
[KeyInstr] Add MIR parser support (#133494)
RFC: https://discourse.llvm.org/t/rfc-improving-is-stmt-placement-for-better-interactive-debugging/82668
Commit: a3f58f3c84901afe296718863aceca45e7a8a86a
https://github.com/llvm/llvm-project/commit/a3f58f3c84901afe296718863aceca45e7a8a86a
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
Log Message:
-----------
[NFC][DebugInfo] Expand coverage of a RISCV test
This is a pre-commit for a patch (#134677) -- the test behaviour is not
being changed, instead I've added "-v" to the llvm-dwarfdump commandline
for --debug-line. This prints out how the linetable is encoded, not just
what the linetable means, and it's important to illustrate that in the
upcoming patch. I've separated out the llvm-dwarfdump line for .debug_info
so that it's not affected by adding -v.
Commit: 2a88feb3947606679453f886d79db611cdaef9fc
https://github.com/llvm/llvm-project/commit/2a88feb3947606679453f886d79db611cdaef9fc
Author: Georgios Pinitas <georgios.pinitas at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Canonicalize slice over overlapped or inside a pad. (#138900)
Update the paddings and/or the slice parameters when a `tosa.slice`
after a `tosa.pad` is accessing only an overlapping or not region of the
padded tensor.
Signed-off-by: Georgios Pinitas <georgios.pinitas at arm.com>
Commit: 160abfb5e623a67014de311a6b50f12e4104f7c9
https://github.com/llvm/llvm-project/commit/160abfb5e623a67014de311a6b50f12e4104f7c9
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-bf16-compares.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add ISel for bfloat scalable vector compares. (#138707)
Commit: a385c47a59e64ce54eb7257f4ec161fa4e112c16
https://github.com/llvm/llvm-project/commit/a385c47a59e64ce54eb7257f4ec161fa4e112c16
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-cancel-distribute-parallel-loop.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] convert wsloop cancellation to LLVMIR (#137194)
Taskloop support will follow in a later patch.
Commit: 8338a3c92ba08cf409a75adbfb212aa06ca66f31
https://github.com/llvm/llvm-project/commit/8338a3c92ba08cf409a75adbfb212aa06ca66f31
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] Convert omp.cancellation_point to LLVMIR (#137205)
This is basically identical to cancel except without the if clause.
taskgroup will be implemented in a followup PR.
Commit: 127f48668b719798770c36a20288ef5230669f42
https://github.com/llvm/llvm-project/commit/127f48668b719798770c36a20288ef5230669f42
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
Log Message:
-----------
[LV] Add test showing incorrect metadata merging when narrowing IGs.
Add test showing that incorrect tbaa metadata is added to the widened
loads and stores when narrowing interleave groups.
The widened loads/stores currently have the TBAA metadata of the first
load/store, even though the wide accesses also access data with types of
the second load/store.
Commit: ce7c1963b914931817dd983f488cc0b810187b3a
https://github.com/llvm/llvm-project/commit/ce7c1963b914931817dd983f488cc0b810187b3a
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/Options.td
M clang/test/Lexer/char8_t.cpp
Log Message:
-----------
[Clang] Ignore -fchar8_t in C (#138716)
In C, `char8_t` is an alias to unsigned char, and should never be a
keyword.
Fixes #55373
Commit: e40200901cf1af860db9ded5c03b7b104396e429
https://github.com/llvm/llvm-project/commit/e40200901cf1af860db9ded5c03b7b104396e429
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/docs/OpenMPSupport.md
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
M mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] cancel(lation point) taskgroup LLVMIR (#137841)
A cancel or cancellation point for taskgroup is always nested inside of
a task inside of the taskgroup. For the task which is cancelled, it is
that task which needs to be cleaned up: not the owning taskgroup.
Therefore the cancellation branch handler is done in the conversion of
the task not in conversion of taskgroup.
I added a firstprivate clause to the test for cancel taskgroup to
demonstrate that the block being branched to is the same block where
mandatory cleanup code is added. Cancellation point follows exactly the
same code path.
Commit: 358ebddeb836d1c0ac665a8a2faa2e07fd89da63
https://github.com/llvm/llvm-project/commit/358ebddeb836d1c0ac665a8a2faa2e07fd89da63
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/unittests/ADT/DenseMapTest.cpp
Log Message:
-----------
[DenseMap] Introduce lookup_or (#138887)
Introduce lookup_or, a variant of lookup, for non-default-constructible
values.
Commit: 4eebc8d003f25adf52a75702d6ee24f69330d920
https://github.com/llvm/llvm-project/commit/4eebc8d003f25adf52a75702d6ee24f69330d920
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Mark various matchers const (NFC) (#138834)
Mark matchers const and remove an extraneous template parameter in
SCEVPatternMatch. Since SCEVPatternMatch is intertwined with
PatternMatch, also fix constness issues there.
Commit: 20169cb4ac328be419033eda26555d2d79898b84
https://github.com/llvm/llvm-project/commit/20169cb4ac328be419033eda26555d2d79898b84
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/unittests/ADT/DenseMapTest.cpp
Log Message:
-----------
[DenseMap] Introduce emplace_or_assign (#138886)
Introduce emplace_or_assign, a variant of insert_or_assign that has
slightly better characteristics.
Commit: b3ef15aa00c94aa937cb40cd7f9483140c62514d
https://github.com/llvm/llvm-project/commit/b3ef15aa00c94aa937cb40cd7f9483140c62514d
Author: Kirill Radkin <116365474+kr-sc at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
Log Message:
-----------
[RISCV] Fix generation of DWARF info for vector segmented types (#137941)
In DWARF info RISC-V Vector types are presented as DW_TAG_array_type
with tags DW_AT_type (what elements does this array consist of) and
DW_TAG_subrange_type. DW_TAG_subrange_type have DW_AT_upper_bound tag
which contain upper bound value for this array.
For now, it's generate same DWARF info about length of segmented types
and their corresponding non-tuple types.
For example, vint32m4x2_t and vint32m4_t have DW_TAG_array_type with
same DW_AT_type and DW_TAG_subrange_type, it means that this types have
same length, which is not correct
(vint32m4x2_t length is twice as big as vint32m4_t)
Commit: 356bd2c9605761121b49f318a187560ec306718e
https://github.com/llvm/llvm-project/commit/356bd2c9605761121b49f318a187560ec306718e
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Allow unsigned types for rescale ops during validation (#138253)
This commit allows unsigned types (ui8/ui16/ui32) when checking for
valid element types, only for rescale operators.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: cedeef6707fc702ed4ba197b3c841edbc688c78e
https://github.com/llvm/llvm-project/commit/cedeef6707fc702ed4ba197b3c841edbc688c78e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Log Message:
-----------
[LSR] Replace casts with an equivalent std::as_const (NFC) (#138980)
The casts / `std::as_const` are used here to select `const` overload of
`begin()`/`end()` so that the type of the returned iterator matches the
type of `J`, which is `const_iterator`.
Commit: 92cc31b0f7737408dffd38c2384dff825abb8e3a
https://github.com/llvm/llvm-project/commit/92cc31b0f7737408dffd38c2384dff825abb8e3a
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.h
A llvm/lib/Target/ARC/ARCSelectionDAGInfo.cpp
A llvm/lib/Target/ARC/ARCSelectionDAGInfo.h
M llvm/lib/Target/ARC/ARCSubtarget.cpp
M llvm/lib/Target/ARC/ARCSubtarget.h
M llvm/lib/Target/ARC/CMakeLists.txt
M llvm/lib/Target/CSKY/CMakeLists.txt
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.h
A llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.cpp
A llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.h
M llvm/lib/Target/CSKY/CSKYSubtarget.cpp
M llvm/lib/Target/CSKY/CSKYSubtarget.h
M llvm/lib/Target/Lanai/CMakeLists.txt
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.h
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
Log Message:
-----------
[ARC][CSKY][Lanai] TableGen-erate SDNode descriptions (#138874)
This consolidates node definitions into one place and enables automatic
node verification.
Part of #119709.
Commit: d9bdc2d6a2d3efcce81ecab151b393f19a81696b
https://github.com/llvm/llvm-project/commit/d9bdc2d6a2d3efcce81ecab151b393f19a81696b
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][Disassembler][NFCI] Always defer immediate operands. (#138885)
Removes the need to parameterise decoders with OperandSemantics,
ImmWidth and MandatoryLiteral.
Likely allows further simplification of handling _DEFERRED immediates.
Tested to work downstream.
Commit: 1484f82cbc62eab9c4c8f393b84c2f521bf882f6
https://github.com/llvm/llvm-project/commit/1484f82cbc62eab9c4c8f393b84c2f521bf882f6
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
Log Message:
-----------
[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)
Split off from #118638, this adds VPInstruction::StepVector, which
generates integer step vectors (0,1,2,...,VF). This is a step towards
eventually modelling all the separate parts of
VPWidenIntOrFpInductionRecipe in VPlan.
This is then used by VPWidenIntOrFpInductionRecipe, where we materialize
it just before unrolling so the operands stay in a fixed position.
The need for a separate operand in VPWidenIntOrFpInductionRecipe, as
well as the need to update it in
optimizeVectorInductionWidthForTCAndVFUF, should be removed with #118638
when everything is expanded in convertToConcreteRecipes.
Commit: c4f723a7c3bb12ce4e247bcaed755c8d927f73a4
https://github.com/llvm/llvm-project/commit/c4f723a7c3bb12ce4e247bcaed755c8d927f73a4
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/pr125278.ll
Log Message:
-----------
[LV] Strip unmaintainable MinBWs assert (#136858)
tryToWiden attempts to replace an Instruction with a Constant from SCEV,
but forgets to erase the Instruction from the MinBWs map, leading to an
assert in VPlanTransforms::truncateToMinimalBitwidths. Going forward,
the assertion in truncateToMinimalBitwidths is unmaintainable, as LV
could simplify the expression at any point: fix the bug by stripping the
unmaintable assertion.
Fixes #125278.
Commit: 067caaafb58a156d0d77229422607782a639f5b5
https://github.com/llvm/llvm-project/commit/067caaafb58a156d0d77229422607782a639f5b5
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
Log Message:
-----------
[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#125885)
AMDGPU scheduler's `PreRARematStage` attempts to increase function
occupancy w.r.t. ArchVGPR usage by rematerializing trivial
ArchVGPR-defining instruction next to their single use. It first
collects all eligible trivially rematerializable instructions in the
function, then sinks them one-by-one while recomputing occupancy in all
affected regions each time to determine if and when it has managed to
increase overall occupancy. If it does, changes are committed to the
scheduler's state; otherwise modifications to the IR are reverted and
the scheduling stage gives up.
In both cases, this scheduling stage currently involves repeated queries
for up-to-date occupancy estimates and some state copying to enable
reversal of sinking decisions when occupancy is revealed not to
increase. The current implementation also does not accurately track
register pressure changes in all regions affected by sinking decisions.
This commit refactors this scheduling stage, improving RP tracking and
splitting the stage into two distinct steps to avoid repeated occupancy
queries and IR/state rollbacks.
- Analysis and collection (`canIncreaseOccupancyOrReduceSpill`). The
number of ArchVGPRs to save to reduce spilling or increase function
occupancy by 1 (when there is no spilling) is computed. Then,
instructions eligible for rematerialization are collected, stopping as
soon as enough have been identified to be able to achieve our goal
(according to slightly optimistic heuristics). If there aren't enough of
such instructions, the scheduling stage stops here.
- Rematerialization (`rematerialize`). Instructions collected in the
first step are rematerialized one-by-one. Now we are able to directly
update the scheduler's state since we have already done the occupancy
analysis and know we won't have to rollback any state. Register
pressures for impacted regions are recomputed only once, as opposed to
at every sinking decision.
In the case where the stage attempted to increase occupancy, and if both
rematerializations alone and rescheduling after were unable to improve
occupancy, then all rematerializations are rollbacked.
Commit: 5f1c55690969046676c049884d8411dde512c909
https://github.com/llvm/llvm-project/commit/5f1c55690969046676c049884d8411dde512c909
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
Log Message:
-----------
[RISCV][test] Precommit test for #137973 simplifyInstruction support
Commit: 0d47a4548c17b320e02e33a1e250792626652e59
https://github.com/llvm/llvm-project/commit/0d47a4548c17b320e02e33a1e250792626652e59
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/include/lldb/DataFormatters/FormattersHelpers.h
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxProxyArray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSliceArray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxValarray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppTuple.cpp
M lldb/source/Plugins/Language/ObjC/NSArray.cpp
M lldb/source/Plugins/Language/ObjC/NSDictionary.cpp
M lldb/source/Plugins/Language/ObjC/NSIndexPath.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
Log Message:
-----------
[lldb][DataFormatters] Change ExtractIndexFromString to return std::optional (#138297)
This PR is in continuation of
https://github.com/llvm/llvm-project/pull/136693.
Commit: 534d221b63bb52f64e1f3ad3c40cfb87323d28ec
https://github.com/llvm/llvm-project/commit/534d221b63bb52f64e1f3ad3c40cfb87323d28ec
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-lowering-diags.ll
Log Message:
-----------
(reland) [GlobalISel] Diagnose inline assembly constraint lowering errors (#139049)
The initial patch (#135782 caused issues because it emits an error, and llc is sensitive to it.
It also caused compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp to fail.
Use warnings instead + reject lowering. That way, the fallback path is used without llc/clang returning a failure code.
If fallback isn't enabled then the warnings provide context as to why lowering failed.
Original commit description for #135782:
Instead of printing something to dbgs (which is not visible to all users),
emit a diagnostic like the DAG does. We still crash later because we fail to
select the inline assembly, but at least now users will know why it's crashing.
In a future patch we could also recover from the error like the DAG does, so the
lowering can keep going until it either crashes or gives a different error later.
Commit: 245def9def7b025644a8cf991ba24c53a50822c6
https://github.com/llvm/llvm-project/commit/245def9def7b025644a8cf991ba24c53a50822c6
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[Clang][NFC] Put potentially expensive check behind NDEBUG
Commit: 52b345d036677e6377ea5e2022a1b6bd403ed91e
https://github.com/llvm/llvm-project/commit/52b345d036677e6377ea5e2022a1b6bd403ed91e
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
Log Message:
-----------
[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after MachineCopyPropagation (#137973)
PR #136875 was posted as a draft PR that handled a subset of these
cases, using the CompressPat mechanism. The consensus from that
discussion (and a conclusion I agree with) is that it would be
beneficial doing this optimisation earlier on, and in a way that isn't
limited just to cases that can be handled by instruction compression.
The most common source for instructions that can be
optimized/canonicalized in this way is through tail duplication in
MachineBlockPlacement followed by machine copy propagation. For RISC-V,
choosing a more canonical instruction allows it to be compressed when it
couldn't be before. There is the potential that it would make other
MI-level optimisations easier.
This modifies ~910 instructions across an llvm-test-suite build
including SPEC2017, targeting rva22u64. Looking at the diff, it seems
there's room for eliminating instructions or further propagating after
this.
Coverage of instructions is based on observations from a script written
to find redundant or improperly canonicalized instructions (though I aim
to support all instructions in a 'group' at once, e.g. MUL* even if I
only saw some variants of MUL in practice).
Commit: d1783406720dc0fd30fec7bb354c37ec307c6e10
https://github.com/llvm/llvm-project/commit/d1783406720dc0fd30fec7bb354c37ec307c6e10
Author: Simi Pallipurath <simi.pallipurath at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[ARM][Compiler-RT] Add optional exclusion of libc provided ARM AEABI builtins from compiler-rt. (#137952)
This patch introduces a new optional CMake flag:
COMPILER_RT_EXCLUDE_LIBC_PROVIDED_ARM_AEABI_BUILTINS
When enabled, this flag excludes the following ARM AEABI memory function
implementations from the compiler-rt build:
__aeabi_memcmp
__aeabi_memset
__aeabi_memcpy
__aeabi_memmove
These functions are already provided by standard C libraries like glibc,
newlib, and picolibc, so excluding them avoids duplicate symbol
definitions and reduces unnecessary code duplication.
Note:
- libgcc does not define the __aeabi_* functions that overlap with those
provided by the C library. Enabling this option makes compiler-rt behave
consistently with libgcc.
- This prevents duplicate symbol errors when linking, particularly in
bare-metal configurations where compiler-rt is linked first.
- This flag is OFF by default, meaning all AEABI memory builtins will
still be built unless explicitly excluded.
This change is useful for environments where libc provides runtime
routines, supporting more minimal, conflict free builds.
Commit: ea7e23c909fe5e82f26665bdd0afdaa70d67721f
https://github.com/llvm/llvm-project/commit/ea7e23c909fe5e82f26665bdd0afdaa70d67721f
Author: Mikhail Zakharov <zmish1993 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/Shell/Expr/TestProcessModificationIdOnExpr.cpp
Log Message:
-----------
[lldb] Fixed TestProcessModificationIdOnExpr to work on both x86 and x64 architectures (#138941)
Original PR where test was introduced and improvements discussed:
https://github.com/llvm/llvm-project/pull/129092#issuecomment-2855337004
Co-authored-by: Mikhail Zakharov <mikhail.zakharov at jetbrains.com>
Commit: c290f48a45df5dc66c9cdc3f3b340cb0e3fc3937
https://github.com/llvm/llvm-project/commit/c290f48a45df5dc66c9cdc3f3b340cb0e3fc3937
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU][NFC] Remove unused operand types. (#139062)
Commit: 41321416815d74a4a7fd15c78fcfa5af457625bb
https://github.com/llvm/llvm-project/commit/41321416815d74a4a7fd15c78fcfa5af457625bb
Author: Ely Ronnen <elyronnen at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/include/lldb/API/SBThreadPlan.h
M lldb/source/API/SBThreadPlan.cpp
M lldb/test/API/functionalities/step_scripted/Steps.py
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
M lldb/test/API/functionalities/step_scripted/main.c
Log Message:
-----------
[lldb] Expose QueueThreadPlanForStepSingleInstruction function to SBThreadPlan (#137904)
Expose `QueueThreadPlanForStepSingleInstruction` function to
SBThreadPlan
Commit: 60d0bc1faeacb8be8ef38457bce0a4f0674bc575
https://github.com/llvm/llvm-project/commit/60d0bc1faeacb8be8ef38457bce0a4f0674bc575
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
A llvm/test/Transforms/CodeGenPrepare/X86/split-dbg.ll
Log Message:
-----------
Propagate DebugLocs on phis in BreakCriticalEdges (#133492)
The pull request discusses whether this change is needed or not. We leant
towards "it can't hurt" on the basis that it's at worst slightly unecessary
(but not incorret).
The motivation for the patch came from reviewing code duplication sites to
update for Key Instructions, finding this, trying to generate a test case and
seeing the DebugLocs aren't propagated.
Commit: 1d3f8f4871a1d46312902307f657f7a239cfa815
https://github.com/llvm/llvm-project/commit/1d3f8f4871a1d46312902307f657f7a239cfa815
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 92cc31b0f7737408dffd38c2384dff825abb8e3a for Lanai
Commit: 5b290588b52c3adbe9bde7d22ed5ae13d299f88e
https://github.com/llvm/llvm-project/commit/5b290588b52c3adbe9bde7d22ed5ae13d299f88e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMP.cpp
Log Message:
-----------
[LLVM][OpenMP] Add older versions to llvm::omp::getOpenMPVersions (#138967)
Add 3.1 and 4.0 as versions. This will make flang's default OpenMP
version (3.1) be included in the list.
Commit: 382a085a95b0abeac77b150b7b644b372bd08e78
https://github.com/llvm/llvm-project/commit/382a085a95b0abeac77b150b7b644b372bd08e78
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
Log Message:
-----------
[AMDGPU] Regenerate mfma-loop.ll test
#125885 did not update the test.
Commit: 8fa3b52ac46cf71e13cc687c77a1a61662675f93
https://github.com/llvm/llvm-project/commit/8fa3b52ac46cf71e13cc687c77a1a61662675f93
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
A llvm/test/DebugInfo/KeyInstructions/X86/cgp-break-critical-edge.ll
A llvm/test/DebugInfo/KeyInstructions/X86/lit.local.cfg
Log Message:
-----------
[KeyInstr] Remap cloned PHIs in BreakCriticalEdges (#133493)
RFC: https://discourse.llvm.org/t/rfc-improving-is-stmt-placement-for-better-interactive-debugging/82668
Commit: e9df48e8a49cbfc82c71c8951a85e11b0cd0102a
https://github.com/llvm/llvm-project/commit/e9df48e8a49cbfc82c71c8951a85e11b0cd0102a
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
R llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-lowering-diags.ll
Log Message:
-----------
Revert "(reland) [GlobalISel] Diagnose inline assembly constraint lowering errors (#139049)"
This reverts commit 534d221b63bb52f64e1f3ad3c40cfb87323d28ec.
Commit: d2fe8896766800a97462599fc7fb557c8d424fa4
https://github.com/llvm/llvm-project/commit/d2fe8896766800a97462599fc7fb557c8d424fa4
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[KeyInstr] Don't propagate source atoms to new uncond br in splitBasicBlock (#139070)
splitBasicBlock inserts an unconditional branch in the "before" block to
the "after" block. It copies the DebugLoc from the split point. Prevent
it copying the source location atom.
Add unittest.
RFC:
https://discourse.llvm.org/t/rfc-improving-is-stmt-placement-for-better-interactive-debugging/82668
Commit: da8d60fbfe4582edd415c8150832a84517f3713b
https://github.com/llvm/llvm-project/commit/da8d60fbfe4582edd415c8150832a84517f3713b
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/UndefinedBehavior.rst
Log Message:
-----------
[docs][nfc] Fix code-formatting in UB docs (#139079)
Commit: 6b37eeed9fe7918f28c6c2fa14788818143c1f80
https://github.com/llvm/llvm-project/commit/6b37eeed9fe7918f28c6c2fa14788818143c1f80
Author: Nico Weber <thakis at chromium.org>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/Lanai/BUILD.gn
Log Message:
-----------
[gn] port Lanai bits of 92cc31b0f773740 (-gen-sd-node-info)
(The GN port does not yet support the ARC and CSKY targets.)
Commit: be6c6e2f902c71f267f91852e3391a5301f949ac
https://github.com/llvm/llvm-project/commit/be6c6e2f902c71f267f91852e3391a5301f949ac
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
Log Message:
-----------
[AMDGPU][True16][MC] run update script on a few disasm tests (#138988)
This is a NFC patch.
Added -mattr=-real-true16 on a few disasm tests and run update script.
This is preparing for the +real-true16 change
Commit: 30f7a6cc42856d2028bfd00321ddb1428e0c46aa
https://github.com/llvm/llvm-project/commit/30f7a6cc42856d2028bfd00321ddb1428e0c46aa
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/allocate-source-allocatables-2.f90
M flang/test/Lower/allocate-source-allocatables.f90
M flang/test/Lower/allocate-source-pointers.f90
A flang/test/Lower/volatile-allocatable.f90
Log Message:
-----------
[flang] Correctly prepare allocatable runtime call arguments (#138727)
When lowering allocatables, the generated calls to runtime functions
were not using the runtime::createArguments utility which handles the
required conversions. createArguments is where I added the implicit
volatile casts to handle converting volatile variables to the
appropriate type based on their volatility in the callee. Because the
calls to allocatable runtime functions were not using this function,
their arguments were not casted to have the appropriate volatility.
Add a test to demonstrate that volatile and allocatable
class/box/reference types are appropriately casted before calling into
the runtime library.
Instead of using a recursive variadic template to perform the
conversions in createArguments, map over the arguments directly so that
createArguments can be called with an ArrayRef of arguments. Some cases
in Allocatable.cpp already had a vector of values at the point where
createArguments needed to be called - the new overload allows calling
with a vector of args or the variadic version with each argument spelled
out at the callsite.
This change resulted in the allocatable runtime calls having their
arguments converted left-to-right, which changed some of the test
results. I used CHECK-DAG to ignore the order.
Add some missing handling of volatile class entities, which I previously
missed because I had not yet enabled volatile class entities in Lower.
Commit: 7548cec16f54d3abf2c1387d743372f589ce290f
https://github.com/llvm/llvm-project/commit/7548cec16f54d3abf2c1387d743372f589ce290f
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M CONTRIBUTING.md
M bolt/Maintainers.txt
M clang-tools-extra/Maintainers.txt
M clang/Maintainers.rst
M clang/www/menu.html.incl
M flang-rt/CODE_OWNERS.TXT
M libcxx/utils/ci/BOT_OWNERS.txt
M llvm/CREDITS.TXT
M llvm/docs/CodeOfConduct.rst
M llvm/docs/DiscourseMigrationGuide.md
Log Message:
-----------
[www][docs] Remove last mentions of IRC (#139076)
It's the end of an era. The IRC channel was previously where the
community gathered to discuss technical topics but is now a ghost town
where the primary activity is moderators (me) kickbanning the same
individual dozens of times a day for CoC violations and the secondary
activity is telling the occasional person to come to Discord for help.
The number of people engaging on IRC for the community's intended
purposes seems to be roughly one person a month.
So this removes all remaining mentions of IRC from our documentation so
that it no longer appears to be an "official" channel for communicating
with the community. It also removes IRC handles from the various
maintainers lists, since those would stand out as confusing
anachronisms.
The IRC channel topic already recommends people come to the Discord
server. There is no way to "shut down" an IRC channel such that it no
longer exists, so the channel will continue to exist on OFTC, but will
be unmoderated.
(This was previously discussed in https://discourse.llvm.org/c/llvm/5
but some mentions persisted.)
Commit: 6e654caabedebeaca599fcc2242a668db51fa9c8
https://github.com/llvm/llvm-project/commit/6e654caabedebeaca599fcc2242a668db51fa9c8
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[DAG] Add wrappers for insert and extract sub-vector [nfc] (#137230)
Mechanical change to introduce the new wrappers, and add enough users to
make the usage pattern clear. Once this lands, I'm going to do a further
pass to adjust more callsites as separate changes.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: 7eafa5bdb78f371f3173d31df4479c8f7f23d8aa
https://github.com/llvm/llvm-project/commit/7eafa5bdb78f371f3173d31df4479c8f7f23d8aa
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
Log Message:
-----------
[KeyInstr] Fix #139070 for empty DebugLocs
Commit: b5674cb7be1b010be181883601a3674ceef38683
https://github.com/llvm/llvm-project/commit/b5674cb7be1b010be181883601a3674ceef38683
Author: Zax <44502668+hapeeeeee at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/include/lldb/Core/SourceManager.h
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
A lldb/test/Shell/Commands/command-list-reach-beginning-of-file.test
A lldb/test/Shell/Commands/command-list-reach-end-of-file.test
Log Message:
-----------
[lldb] print a notice when `source list` paging reaches the end of th… (#137515)
Commit: 5f9fd475a03363db6da069b6ded1c503833a695c
https://github.com/llvm/llvm-project/commit/5f9fd475a03363db6da069b6ded1c503833a695c
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/raise-memref.mlir
Log Message:
-----------
[mlir][affine] allow iter args as valid dims (#139069)
that is effectivevely a revert of
7aabf47522625e227433cc9603e0b6858c5dd66d for
mlir/lib/Dialect/Affine/IR/AffineOps.cpp
there are situations when iter args can be used as a dims. For example
in
https://github.com/google/heir/blob/main/lib/Dialect/Polynomial/Conversions/PolynomialToModArith/PolynomialToModArith.cpp#L1036
rootExp and batchSize are iter args that are being used as dims and from
the point of internal loops
they are fixed.
Commit: 3ed158fab432fd92b9d3d1386477ae12fa493132
https://github.com/llvm/llvm-project/commit/3ed158fab432fd92b9d3d1386477ae12fa493132
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/docs/OpenMPSupport.md
Log Message:
-----------
[flang][docs][OpenMP] array sections with DEPEND are supported (#139081)
This was added in
- https://github.com/llvm/llvm-project/pull/132230
- https://github.com/llvm/llvm-project/pull/132994
- https://github.com/llvm/llvm-project/pull/133892
Commit: eb5280938bf282053e1b3d281d45b522f1cdcc2e
https://github.com/llvm/llvm-project/commit/eb5280938bf282053e1b3d281d45b522f1cdcc2e
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
Log Message:
-----------
[NVPTX] Fixup AutoUpgrade of llvm.nvvm.atomic.load.{inc,dec}.32 (#138907)
The previous implementation failed to account for the fact that these
intrinsics have an overloaded pointer type. This version handles the
pointer type and adds tests for llvm.nvvm.atomic.load.add.{f32,f64}.
Commit: 78e573499eb3bc0200db462c356a6523e6ba8000
https://github.com/llvm/llvm-project/commit/78e573499eb3bc0200db462c356a6523e6ba8000
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicInst.h
Log Message:
-----------
[IR] Remove MemSetPatternIntrinsic class [nfc] (#138888)
This class appears to serve no purpose. It looks to be modeled after the
MemIntrinsic/MemTransferInst family of classes, but right now, we only
have a single intrinsic in this "family".
Commit: bbafa5214e8d5d5daf7cf428780500b13a7d6cbb
https://github.com/llvm/llvm-project/commit/bbafa5214e8d5d5daf7cf428780500b13a7d6cbb
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
Log Message:
-----------
[lldb] Fix asan failure in MinidumpFileBuilder
As per comment in https://github.com/llvm/llvm-project/pull/138698#issuecomment-2860369432
Commit: cb0b9614f8ca7ffcd5f091b1c9990adfd6cb7e33
https://github.com/llvm/llvm-project/commit/cb0b9614f8ca7ffcd5f091b1c9990adfd6cb7e33
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
Log Message:
-----------
[lldb] Disable test using GetControlFlowKind on arm
This is only implemented for x86.
Originally introduced in: https://github.com/llvm/llvm-project/pull/137904
Commit: 55517f5f4495968d01100aa00d63db7842842270
https://github.com/llvm/llvm-project/commit/55517f5f4495968d01100aa00d63db7842842270
Author: Finn Plummer <canadienfinn at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/include/clang/Lex/HLSLRootSignatureTokenKinds.def
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/unittests/Lex/LexHLSLRootSignatureTest.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
Log Message:
-----------
[HLSL][RootSignature] Add parsing for empty RootConstants (#137999)
- defines the empty RootConstants in-memory struct
- adds test harness for testing it
- adds missing parameter keywords to the lexer (`RootConstants`,
`num32BitConstants`)
First part of implementing:
https://github.com/llvm/llvm-project/issues/126576
Commit: 9c4c2426d5f3cf5128d544482c939f56c1f2911d
https://github.com/llvm/llvm-project/commit/9c4c2426d5f3cf5128d544482c939f56c1f2911d
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
Log Message:
-----------
[MemProf] Fix bug introduced by restructuring in optional handling (#139092)
The restructuring of the context pruning patch in PR138792
(764614e6355e214c6b64c715d105007b1a4b97fd) introduced a bug under the
non-default -memprof-keep-all-not-cold-contexts handling.
Added more testing of this mode which would have caught the issue.
While here, fix the newly added function name to match code style.
Commit: 2ec08836d1fd78e9efcdfd6f1307f35c8ec633e7
https://github.com/llvm/llvm-project/commit/2ec08836d1fd78e9efcdfd6f1307f35c8ec633e7
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/Mips.cpp
R clang/test/Driver/mips-cpus.c
M llvm/lib/Target/Mips/Mips.td
M llvm/test/CodeGen/Mips/msa/arithmetic.ll
Log Message:
-----------
Revert "[MIPS] Add FeatureMSA to i6400 and i6500 cores (#134985)"
This reverts commit 55a88cdf53948e7460d9c6892f6c481480faa021.
Breaks Sanitizer bot: https://lab.llvm.org/buildbot/#/builders/94/builds/6923
Commit: 155bf37ad995fa07baf99ad59294ec5fe2777635
https://github.com/llvm/llvm-project/commit/155bf37ad995fa07baf99ad59294ec5fe2777635
Author: John Harrison <harjohn at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/tools/lldb-dap/Handler/ContinueRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
Log Message:
-----------
[lldb-dap] Migrate 'continue' request to new RequestHandler. (#138987)
This adds types for the 'continue' request and updates the existing
handler to the new base class.
Commit: 850d96e63a611c46313a5448cd49197d9295ce5f
https://github.com/llvm/llvm-project/commit/850d96e63a611c46313a5448cd49197d9295ce5f
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/CodeGen/CGObjC.cpp
M clang/test/CodeGenObjCXX/arc-rv-attr.mm
Log Message:
-----------
[ObjC] Also enable ARC attachedcall operand bundle for arm64_32. (#138677)
It was enabled for "aarch64", which covers arm64e but not arm64_32.
Co-authored-by: Ahmed Bougacha <ahmed at bougacha.org>
Commit: 2017831d449774e792692aac88721e409ba475e4
https://github.com/llvm/llvm-project/commit/2017831d449774e792692aac88721e409ba475e4
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
Log Message:
-----------
[clang][Unit Test] Updating Negative Stat Caching Diagnostic Unit Test (#138955)
This PR makes a minor modification to make it more stable. The only
change is adding a suffix to the path under test.
rdar://149147920
Commit: f2bc7b75dd3518b6d7dc764b34ca43c1fbc2c22d
https://github.com/llvm/llvm-project/commit/f2bc7b75dd3518b6d7dc764b34ca43c1fbc2c22d
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
Log Message:
-----------
[AArch64] Allow the clang.arc.attachedcall marker to be optional (#138694)
Now that the clang.arc.attachedcall bundle requires having an operand,
which we emit a call to in the RVMARKER sequence, we can achieve our
real goal: make the marker NOP optional.
The intention is that a new ObjC runtime call will be introduced, which
doesn't require the NOP to be present, but must be adjacent to the
possibly-autorelease-returning call (that the bundle is attached to).
This is achieved by having ISel embed whether the marker is necessary
with an additional boolean target immediate operand.
Co-authored-by: Ahmed Bougacha <ahmed at bougacha.org>
Commit: 37fecfaa63eef7bd9dff9c16d74e61c99e3ce70a
https://github.com/llvm/llvm-project/commit/37fecfaa63eef7bd9dff9c16d74e61c99e3ce70a
Author: Vivian Zhang <zhyuhang88 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Log Message:
-----------
[mlir] Support rank-reduced extract_slice in ExtractSliceOfPadTensorSwapPattern (#138921)
This PR fixes `ExtractSliceOfPadTensorSwapPattern` to support
rank-reducing `tensor.extract_slice` ops, which were previously
unhandled and could cause crashes. To support this, an additional
`tensor.extract_slice` is inserted after `tensor.pad` to reduce the
result rank.
Commit: 9c88b6d6898812c01c82a6d5ec991fb331aef015
https://github.com/llvm/llvm-project/commit/9c88b6d6898812c01c82a6d5ec991fb331aef015
Author: Lewis Crawford <lcrawford at nvidia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
M llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
Log Message:
-----------
[ConstantFolding] Fold maximumnum and minimumnum (#138700)
Add constant-folding support for the maximumnum and minimumnum
intrinsics, and extend the tests to show the qnan vs snan behavior
differences between maxnum/maximum/maximumnum.
Commit: 5b7ccdc2a29f3be4b01f0eadca8f52d5dcdd9846
https://github.com/llvm/llvm-project/commit/5b7ccdc2a29f3be4b01f0eadca8f52d5dcdd9846
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM][Maintainers] Step down as an `NVPTX` maintainer (#138936)
Commit: 64bb60a471a5ddc9c9bec413c65fdab730a1e4b0
https://github.com/llvm/llvm-project/commit/64bb60a471a5ddc9c9bec413c65fdab730a1e4b0
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/Lex/ModuleMap.cpp
M clang/test/Modules/Inputs/submodules/module.modulemap
M clang/test/Modules/missing-header.m
Log Message:
-----------
[Modules] Don't fail when an unused textual header is missing. (#138227)
According to the documentation
> A header declaration that does not contain `exclude` nor `textual`
specifies a header that contributes to the enclosing module.
Which means that `exclude` and `textual` header don't contribute to the
enclosing module and their presence isn't required to build such a
module. The keywords tell clang how a header should be treated in a
context of the module but they don't add headers to the module.
When a textual header *is* used, clang still emits "file not found"
error pointing to the location where the missing file is included.
Commit: 5c6cbe25175be37ffa1c809f5163ab7aebecef1a
https://github.com/llvm/llvm-project/commit/5c6cbe25175be37ffa1c809f5163ab7aebecef1a
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/X86.cpp
M clang/test/Driver/x86-mabi.c
Log Message:
-----------
[clang] UEFI default ABI (#138364)
Set MS ABI as default ABI for UEFI.
Commit: 45cd708184e114bb771330d51ec552f7f674ffa0
https://github.com/llvm/llvm-project/commit/45cd708184e114bb771330d51ec552f7f674ffa0
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/source/Core/CoreProperties.td
M lldb/test/API/functionalities/statusline/TestStatusline.py
Log Message:
-----------
[lldb] Change the statusline format to print "no target" (#139021)
Change the default statusline format to print "no target" when lldb is
launched without a target. Currently, the statusline is empty, which
looks rather odd.
Commit: 7c366b041cd0effdcf0b7e1f3a7ad4eb39800349
https://github.com/llvm/llvm-project/commit/7c366b041cd0effdcf0b7e1f3a7ad4eb39800349
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/is_fpclass.ll
Log Message:
-----------
[DirectX] Implement `llvm.is.fpclass` lowering for the fcNegZero FPClassTest and the `IsNaN`, `IsInf`, `IsFinite`, `IsNormal` DXIL ops (#138048)
Fixes #137209
This PR:
- Adds a case to `expandIntrinsic()` in `DXILIntrinsicExpansion.cpp` to
expand the `Intrinsic::is_fpclass` in the case of
`FPClassTest::fcNegZero`
- Defines the `IsNaN`, `IsFinite`, `IsNormal` DXIL ops in `DXIL.td`
- Adds a case to `lowerIntrinsics()` in `DXILOpLowering.cpp` to handle
the lowering of `Intrinsic::is_fpclass` to the DXIL ops `IsNaN`,
`IsInf`, `IsFinite`, `IsNormal` when the FPClassTest is `fcNan`,
`fcInf`, `fcFinite`, and `fcNormal` respectively
- Creates a test `llvm/test/CodeGen/DirectX/is_fpclass.ll` to exercise
the intrinsic expansion and DXIL op lowering of `Intrinsic::is_fpclass`
~~A separate PR will be made to remove the now-redundant `dx_isinf`
intrinsic to address #87777.~~
A proper implementation for the lowering of the `llvm.is.fpclass`
intrinsic to handle all possible combinations of FPClassTest can be
implemented in a separate PR. This PR's implementation focuses primarily
on addressing the current use-cases for DirectML and HLSL intrinsics.
Commit: 808a5f15d7855f78a837c20e866cf4d0b1b90ab2
https://github.com/llvm/llvm-project/commit/808a5f15d7855f78a837c20e866cf4d0b1b90ab2
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-store.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
Log Message:
-----------
[RISCV] Remove`riscv.segN.load/store` in favor of their mask variants (#137045)
RISCVVectorPeepholePass would replace instructions with all-ones mask
with their unmask variant, so there isn't really a point to keep
separate versions of intrinsics.
Note that `riscv.segN.load/store.mask` does not take pointer type (i.e.
address space) as part of its overloading type signature, because RISC-V
doesn't really use address spaces other than the default one.
Commit: e9702ce18a4c40e226da9ac663a6767f8f64569f
https://github.com/llvm/llvm-project/commit/e9702ce18a4c40e226da9ac663a6767f8f64569f
Author: David Green <david.green at arm.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/icmp-or-load.ll
Log Message:
-----------
[AArch64] Add some tests for icmp eq chains of loads. NFC
Commit: 7f633b583eb8ae84190ff2142005222d36c38b6a
https://github.com/llvm/llvm-project/commit/7f633b583eb8ae84190ff2142005222d36c38b6a
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
Log Message:
-----------
[AMDGPU][True16][MC] add true16 mode on a few disasm tests (#139094)
This is a NFC patch.
applied "+real-true16" on a few disasm test and run update script
Commit: cf2f558501ecd4b1985cd34a06d90796c2a891c6
https://github.com/llvm/llvm-project/commit/cf2f558501ecd4b1985cd34a06d90796c2a891c6
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[DAG/RISCV] Continue mitgrating to getInsertSubvector and getExtractSubvector
Follow up to 6e654caab, use the new routines in more places. Note that
I've excluded from this patch any case which uses a getConstant index
instead of a getVectorIdxConstant index just to minimize room for
error. I'll get those in a separate follow up.
Commit: b0bf48d44e5502092c55ea7f353f8c4100635601
https://github.com/llvm/llvm-project/commit/b0bf48d44e5502092c55ea7f353f8c4100635601
Author: Tom Tromey <tromey at adacore.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/IR/DIBuilder.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
A llvm/test/DebugInfo/Generic/discriminant-member.ll
Log Message:
-----------
Two DWARF variant part improvements (#138953)
This patch adds a couple of improvements to the LLVM emission of DWARF
variant parts. One of these is desirable for Ada, and the other is
required.
Currently, when emitting a discriminant, LLVM follows the precise letter
of the DWARF standard, which says:
If the variant part has a discriminant, the discriminant is
represented by a separate debugging information entry which is a
child of the variant part entry.
However, for Ada this does not really make sense. In Ada, the
discriminant field exists outside of any variant part, and it makes more
sense to emit it separately rather than redundantly emit the field once
for each variant part.
This extension was arrived at when this was implemented in GCC, and was
accepted for DWARF 6, see:
https://dwarfstd.org/issues/180123.1.html
Here the patch simply lifts this restriction: if the discriminant field
was already emitted, it isn't re-emitted. This approach allows the Ada
compiler to do what it needs without affecting the Rust output.
Second, this patch extends the discriminant to allow multiple values.
This is needed by Ada. Here, I chose to use a ConstantDataArray of pairs
of integers, with each pair representing a range, as Ada also allows
ranges here. This seemed like a reasonably convenient representation.
Commit: d1da41bf4d271fd9abb9aba37873755feb99e4b6
https://github.com/llvm/llvm-project/commit/d1da41bf4d271fd9abb9aba37873755feb99e4b6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
Log Message:
-----------
[ubsan_minimal] Add __ubsan_report_error_fatal (#138999)
Override may need to know if sanitizer in recover mode.
Commit: a2b28a68125c5e179df01ed62ca8549bcb9c73b1
https://github.com/llvm/llvm-project/commit/a2b28a68125c5e179df01ed62ca8549bcb9c73b1
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[DAG/RISCV] Continue mitgrating to getInsertSubvector and getExtractSubvector
Follow up to 6e654caab and cf2f5585. I'd apparently missed two cases.
Commit: 3bc3b1c6c0f35bf223c595f8426f6726d64553e7
https://github.com/llvm/llvm-project/commit/3bc3b1c6c0f35bf223c595f8426f6726d64553e7
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[HLSL][NFC] Rename isImplicit() to hasRegisterStot() on HLSLResourceBindingAttr (#138964)
Renaming because the name `isImplicit` is ambiguous. It can mean
implicit attribute or implicit binding.
Commit: 81786b9185fc048a3ea83e57f825ec0284e988a8
https://github.com/llvm/llvm-project/commit/81786b9185fc048a3ea83e57f825ec0284e988a8
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV][NFC] Remove unused variable
Remove unused variable in RISCVTargetLowering
Commit: 339dc9500b90dba47e5c7bc9804a4d5f01d592ea
https://github.com/llvm/llvm-project/commit/339dc9500b90dba47e5c7bc9804a4d5f01d592ea
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
Log Message:
-----------
[VPlan] Retain exit conditions and edges in initial VPlan (NFC). (#137709)
Update initial VPlan construction to include exit conditions and edges.
The loop region is now first constructed without entry/exiting. Those
are set after inserting the region in the CFG, to preserve the original
predecessor/successor order of blocks.
For now, all early exits are disconnected before forming the regions,
but a follow-up will update uncountable exit handling to also happen
here. This is required to enable VPlan predication and remove the
dependence any IR BBs
(https://github.com/llvm/llvm-project/pull/128420).
PR: https://github.com/llvm/llvm-project/pull/137709
Commit: 9692dff7b7624208f482007c3b76c838b12fda63
https://github.com/llvm/llvm-project/commit/9692dff7b7624208f482007c3b76c838b12fda63
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/TableGen/cc-assign-to-reg-tuple.td
M llvm/utils/TableGen/CallingConvEmitter.cpp
Log Message:
-----------
[TableGen][NFC] Use early exit to simplify large block in emitAction. (#138220)
Most of the processing in emitAction is in an unneeded else-block--
reduce indentation by exiting after the recursive call.
`XXXGenCallingConv.inc` are identical before and after this patch for
all targets.
Commit: 53e8ff13bd3c1061af01a1508881575db81ce900
https://github.com/llvm/llvm-project/commit/53e8ff13bd3c1061af01a1508881575db81ce900
Author: Zhuoran Yin <zhuoryin at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/test/Dialect/AMDGPU/transfer-read-to-load.mlir
M mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
Log Message:
-----------
[MLIR] Fixing the memref linearization size computation for non-packed memref (#138922)
Credit to @krzysz00 who discovered this subtle bug in `MemRefUtils`. The
problem is in `getLinearizedMemRefOffsetAndSize()` utility. In
particular, how this subroutine computes the linearized size of a memref
is incorrect when given a non-packed memref.
### Background
As context, in a packed memref of `memref<8x8xf32>`, we'd compute the
size by multiplying the size of dimensions together. This is implemented
by composing an affine_map of `affine_map<()[s0, s1] -> (s0 * s1)>` and
then computing the result of size via `%size = affine.apply #map()[%c8,
%c8]`.
However, this is wrong for a non-packed memref of `memref<8x8xf32,
strided<[1024, 1]>>`. Since the previous computed multiplication map
will only consider the dimension sizes, it'd continue to conclude that
the size of the non-packed memref to be 64.
### Solution
This PR come up with a fix such that the linearized size computation
take strides into consideration. It computes the maximum of (dim size *
dim stride) for each dimension. We'd compute the size via the affine_map
of `affine_map<()[stride0, size0, stride1] -> ((stride0 * size0), 1 *
size1)>` and then computing the size via `%size = affine.max
#map()[%stride0, %size0, %size1]`. In particular for the new non-packed
memref, the size will be derived as max(1024\*8, 1\*8) = 8192 (rather
than the wrong size 64 computed by packed memref equation).
Commit: 0beb2f56f6f6eb5aab142334a47228cbbc86c22f
https://github.com/llvm/llvm-project/commit/0beb2f56f6f6eb5aab142334a47228cbbc86c22f
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/max-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/min-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl
Log Message:
-----------
[HLSL][NFC] Stricter Overload Tests (clamp,max,min,pow) (#138993)
Partial implementation of #138016 to unblock other ongoing work. NFC
Commit: 09c80e2944967332c4d889ef19a001ebb4521782
https://github.com/llvm/llvm-project/commit/09c80e2944967332c4d889ef19a001ebb4521782
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/attr-trivial-abi.cpp
M clang/test/SemaCXX/ptrauth-triviality.cpp
M clang/test/SemaCXX/type-traits-nonobject.cpp
Log Message:
-----------
Reland [Clang] Deprecate `__is_trivially_relocatable` (#139061)
The C++26 standard relocatable type traits has slightly different
semantics, so we introduced a new
``__builtin_is_cpp_trivially_relocatable``
when implementing trivial relocation in #127636.
However, having multiple relocatable traits would be confusing
in the long run, so we deprecate the old trait.
As discussed in #127636
`__builtin_is_cpp_trivially_relocatable` should be used instead.
Commit: 9d907a2bb1d2ce67ae4d203218df380a45abaf30
https://github.com/llvm/llvm-project/commit/9d907a2bb1d2ce67ae4d203218df380a45abaf30
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
Log Message:
-----------
AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (#128911)
Update the f64 to f16 lowering for targets which support f16 types.
For unsafe mode, lowered to two FP_ROUND. (This patch
https://reviews.llvm.org/D154528 stops from combining these two FP_ROUND
back). In safe mode, select LowerF64ToF16 (round-to-nearest-even
rounding mode)
Commit: 3a5af231fd3af4b5890ed28f7792b17e56386ffd
https://github.com/llvm/llvm-project/commit/3a5af231fd3af4b5890ed28f7792b17e56386ffd
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
Log Message:
-----------
[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)
Current behavior crashes the compiler.
This bug was found using the AMDGPU Fuzzing project.
Fixes SWDEV-508816.
Commit: 7a6674622603c76274959a9797c0fafb4bc84c44
https://github.com/llvm/llvm-project/commit/7a6674622603c76274959a9797c0fafb4bc84c44
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
Log Message:
-----------
[mlir][xegpu] Handle scalar uniform ops in SIMT distribution. (#138593)
This PR adds support for moving scalar uniform (gpu index ops, constants
etc) outside the `gpu.warp_execute_on_lane0` op. These kinds of ops do
not require distribution and are safe to move out of the warp op. This
also avoid adding separate distribution patterns for these ops.
Example:
```
%1 = gpu.warp_execute_on_lane_0(%laneid) -> (index) {
...
%block_id_x = gpu.block_id x
gpu.yield %block_id_x
}
// use %1
```
To:
```
%block_id_x = gpu.block_id x
%1 = gpu.warp_execute_on_lane_0(%laneid) -> (index) {
...
gpu.yield %block_id_x
}
// use %1
```
Commit: 7feba5febf3a431caf97adc10829f781363e961c
https://github.com/llvm/llvm-project/commit/7feba5febf3a431caf97adc10829f781363e961c
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/vector-ext.cpp
M clang/test/CIR/CodeGen/vector.cpp
M clang/test/CIR/IR/vector.cir
Log Message:
-----------
[CIR] Upstream extract op for VectorType (#138413)
This change adds extract op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
Commit: 71f8f2b1554b0a34abe4f14bcceadebfbf687739
https://github.com/llvm/llvm-project/commit/71f8f2b1554b0a34abe4f14bcceadebfbf687739
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][NFC] Get rid of OPW constants. (#139074)
We can infer the widths from register classes and represent them as
numbers.
Commit: a7b5c303dceb5790b925ac8a019bd66344abb814
https://github.com/llvm/llvm-project/commit/a7b5c303dceb5790b925ac8a019bd66344abb814
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/include/mlir/IR/Builders.h
Log Message:
-----------
Remove unused forward decl (#139108)
Commit: b836f96b8f51daa76f6387de364603db0fe553a7
https://github.com/llvm/llvm-project/commit/b836f96b8f51daa76f6387de364603db0fe553a7
Author: Lei Wang <wlei at fb.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/docs/UsersManual.rst
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/ProfileList.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/profile-filter.c
M clang/test/Driver/fprofile-generate-cold-function-coverage.c
Log Message:
-----------
[Coverage] Support -fprofile-list for cold function coverage (#136333)
Add a new instrumentation section type `[sample-coldcov]` to
support`-fprofile-list` for sample pgo based cold function coverage.
Note that the current cold function coverage is based on sampling PGO
pipeline, which is incompatible with the existing [llvm] option(see
[PGOOptions](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/PGOOptions.h#L27-L43)),
so we can't reuse the IR-PGO(-fprofile-instrument=llvm) flag.
Commit: 254c13d872ea378f9e5569060e24c134d37a0ecb
https://github.com/llvm/llvm-project/commit/254c13d872ea378f9e5569060e24c134d37a0ecb
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/BinarySection.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Passes/PatchEntries.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/AArch64/lite-mode.s
M bolt/unittests/Core/BinaryContext.cpp
Log Message:
-----------
[BOLT][AArch64] Patch functions targeted by optional relocs (#138750)
On AArch64, we create optional/weak relocations that may not be
processed due to the relocated value overflow. When the overflow
happens, we used to enforce patching for all functions in the binary via
--force-patch option. This PR relaxes the requirement, and enforces
patching only for functions that are target of optional relocations.
Moreover, if the compact code model is used, the relocation overflow is
guaranteed not to happen and the patching will be skipped.
Commit: c526683c7f2cf94c9e3a55cc810a0bb90e68c646
https://github.com/llvm/llvm-project/commit/c526683c7f2cf94c9e3a55cc810a0bb90e68c646
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
Log Message:
-----------
[MemProf] Simplify unittest save and restore of options (#139117)
Address post-commit review feedback for PR139092 (and fix another
instance of the same code). Save and restore option values via a saved
bool value, instead of invoking cl::ResetAllOptionOccurrences.
Commit: 8c61befff8e8687e7848fb1044beb20b41503451
https://github.com/llvm/llvm-project/commit/8c61befff8e8687e7848fb1044beb20b41503451
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
Log Message:
-----------
GlobalISel: Translate minimumnum and maximumnum (#139106)
Commit: 54bb2295c31323a77e018ceb2c737d28bd0a5986
https://github.com/llvm/llvm-project/commit/54bb2295c31323a77e018ceb2c737d28bd0a5986
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Migrate getConstant indexed insert/extract subvector to new API (#139111)
Note that this change is possibly not NFC. The prior routines used
getConstant with XLenVT. The new wrappers will used getVectorIdxConstant
instead. Digging through the code, the type used for the index will be
the integer of pointer width from DL. For typical RV32 and RV64
configurations the pointer will be of equal width to XLEN, but you could
have a 32b pointer on an RV64 machine.
Commit: 652ab9800808c254bbd84d81d4583c13cd073abb
https://github.com/llvm/llvm-project/commit/652ab9800808c254bbd84d81d4583c13cd073abb
Author: David Sankel <camior at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lld/ELF/Options.td
Log Message:
-----------
[lld][NFC] Fix minor typo in docs (#138898)
Commit: 7f98e5a5ea12b986b8637da22b46544b95f831cf
https://github.com/llvm/llvm-project/commit/7f98e5a5ea12b986b8637da22b46544b95f831cf
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
Log Message:
-----------
[MLIR][LLVM] Fix llvm.mlir.global mismatching print and parser order (#138986)
`GlobalOp` was parsing `thread_local` after `unnamed_addr`, but printing in the reverse order.
While here, make `AliasOp` match the same behavior and share common parts of global and alias printing.
Commit: 5fe69fd95c4e2bc55a41a41047d08522a5f26d57
https://github.com/llvm/llvm-project/commit/5fe69fd95c4e2bc55a41a41047d08522a5f26d57
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/test/Transforms/DoConcurrent/basic_device.mlir
M flang/test/Transforms/DoConcurrent/basic_host.f90
M flang/test/Transforms/DoConcurrent/basic_host.mlir
M flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90
R flang/test/Transforms/DoConcurrent/loop_nest_test.f90
M flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90
M flang/test/Transforms/DoConcurrent/non_const_bounds.f90
M flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90
Log Message:
-----------
[flang][OpenMP] Update `do concurrent` mapping pass to use `fir.do_concurrent` op (#138489)
This PR updates the `do concurrent` to OpenMP mapping pass to use the
newly added `fir.do_concurrent` ops that were recently added upstream
instead of handling nests of `fir.do_loop ... unordered` ops.
Parent PR: https://github.com/llvm/llvm-project/pull/137928.
Commit: 21130d3f068ae5d9f3d11750f5a3bcf63ed36082
https://github.com/llvm/llvm-project/commit/21130d3f068ae5d9f3d11750f5a3bcf63ed36082
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] One last migration to getInsertSubvector [nfc]
Commit: ae6e1276233ca541fdb2be1dde3074eb78277859
https://github.com/llvm/llvm-project/commit/ae6e1276233ca541fdb2be1dde3074eb78277859
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/str-narrow-zero-merge.mir
Log Message:
-----------
[AArch64] Merge scaled and unscaled narrow zero stores (#136705)
Commit: 8a7b5012c26f6db060bf5c472fc9fb54f37ecf65
https://github.com/llvm/llvm-project/commit/8a7b5012c26f6db060bf5c472fc9fb54f37ecf65
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
Log Message:
-----------
[MemProf] Fix summary bitcode record description (NFC) (#139127)
Commit 776476c282bca71d5b856e80e0a88fbd6f3ccdd2 (PR117404), which
introduced the radix tree representation of allocation context summary
records, incorrectly changed the description of the
FS_COMBINED_CALLSITE_INFO record instead of the intended
FS_COMBINED_ALLOC_INFO record.
Commit: d7987f1ce9bdc57fe10de6eef25fbe0df725c68f
https://github.com/llvm/llvm-project/commit/d7987f1ce9bdc57fe10de6eef25fbe0df725c68f
Author: Aleksandar Zecevic <azecevic at tenstorrent.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributeInterfaces.td
Log Message:
-----------
[mlir][memref] Fix typo in `BuiltinAttributeInterfaces` description (#136774)
Commit: 515b4a4fdd7ac97373b68850a2ffa72e2b8e9178
https://github.com/llvm/llvm-project/commit/515b4a4fdd7ac97373b68850a2ffa72e2b8e9178
Author: Ian Anderson <iana at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Job.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Lex/InitHeaderSearch.cpp
A clang/test/Driver/Inputs/DriverKit19.0.sdk/System/DriverKit/System/Library/SubFrameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/Library/Frameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/System/Library/Frameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/System/Library/SubFrameworks/.keep
A clang/test/Driver/darwin-framework-search-paths.c
R clang/test/Driver/darwin-subframeworks.c
M clang/test/Driver/driverkit-path.c
R clang/test/Preprocessor/cuda-macos-includes.cu
M clang/unittests/Frontend/CMakeLists.txt
A clang/unittests/Frontend/SearchPathTest.cpp
Log Message:
-----------
[clang][Darwin] Remove legacy framework search path logic in the frontend (#138234)
Move the Darwin framework search path logic from
InitHeaderSearch::AddDefaultIncludePaths to
DarwinClang::AddClangSystemIncludeArgs. Add a new -internal-iframework
cc1 argument to support the tool chain adding these paths.
Now that the tool chain is adding search paths via cc1 flag, they're
only added if they exist, so the Preprocessor/cuda-macos-includes.cu
test is no longer relevant.
Change Driver/driverkit-path.c and Driver/darwin-subframeworks.c to do
-### style testing similar to the darwin-header-search and
darwin-embedded-search-paths tests. Rename darwin-subframeworks.c to
darwin-framework-search-paths.c and have it test all framework search
paths, not just SubFrameworks.
Add a unit test to validate that the myriad of search path flags result
in the expected search path list.
Fixes https://github.com/llvm/llvm-project/issues/75638
Commit: 88e68872fd34da9c778e2969e9bf9200bc47fab6
https://github.com/llvm/llvm-project/commit/88e68872fd34da9c778e2969e9bf9200bc47fab6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 515b4a4fdd7a
Commit: 227e1ff73b6c0cbdd912c69405777f7121dc0760
https://github.com/llvm/llvm-project/commit/227e1ff73b6c0cbdd912c69405777f7121dc0760
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/do_concurrent.fir
M flang/test/Fir/invalid.fir
Log Message:
-----------
[flang][fir] Add locality specifiers modeling to `fir.do_concurrent.loop` (#138506)
Commit: a861f50030a9dac28a35654506bb28d2bc239b56
https://github.com/llvm/llvm-project/commit/a861f50030a9dac28a35654506bb28d2bc239b56
Author: Ralender <Tyker1 at outlook.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/CodeGen/WinEHPrepare.cpp
M llvm/test/CodeGen/WinEH/wineh-asm.ll
A llvm/test/CodeGen/WinEH/wineh-asm2.ll
Log Message:
-----------
[WinEH] Fix asm in catchpad being turned into unreachable (#138392)
Commit: d06d43a9e8cb5db84e6ee3557b6244e14a291def
https://github.com/llvm/llvm-project/commit/d06d43a9e8cb5db84e6ee3557b6244e14a291def
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
Log Message:
-----------
[VPlan] Add printPhiOperands to VPPhiAccessors, use for wide phis.
(NFC modulo debug output changes)
Add generic helper to print phi operands (incoming values) together with
their incoming blocks.
As more and more transforms are added, keeping the incoming blocks of
phis becomes more important. Print incoming blocks via VPPhiAcessors, to
make debugging easier.
Commit: 02f61ab46b1608c26fd72862d4b46cbb7b034889
https://github.com/llvm/llvm-project/commit/02f61ab46b1608c26fd72862d4b46cbb7b034889
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/designators-component-ref.f90
Log Message:
-----------
[flang] Use box for components with non-default lower bounds (#138994)
When designating an array component that has non-default lower bounds
the bridge was producing hlfir designates yielding reference types,
which did not preserve the bounds information. Then, when creating
components, unadjusted indices were used when initializing the
structure.
We could look at the declaration to get the shape parameter, but this
would not be preserved if the component were passed as a block argument.
These results must be boxed, but we also must not lose the contiguity
information either. To address contiguity, annotate these boxes with the
`contiguous` attribute during designation.
Note that other designated entities are handled inside the
HlfirDesignatorBuilder while component designators are built in
HlfirBuilder. I am not sure if this handling should be moved into the
designator builder or left in the general builder, so feedback is
welcome.
Also, I wouldn't mind finding a test that demonstrates a box-designated
component with the contiguous attribute really is determined to be
contiguous by any passes down the line checking for that. I don't have a
test like that yet.
Commit: 28156539a9df3fa0d9db47c405c0006fcee9f77f
https://github.com/llvm/llvm-project/commit/28156539a9df3fa0d9db47c405c0006fcee9f77f
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
Log Message:
-----------
[lldb] Disable test using GetControlFlowKind on arm
Commit: e7dcf1b7e5574d03d1ce6e7520d5683cfea37706
https://github.com/llvm/llvm-project/commit/e7dcf1b7e5574d03d1ce6e7520d5683cfea37706
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
Log Message:
-----------
[mlir][xegpu] Add SIMT distribution patterns for UpdateNdOffset and PrefetchNd ops. (#138033)
This PR adds support for SIMT distribution of UpdateNdOffset and
PrefetchNd ops.
For both these ops distribution will remove the layout attribute from
the tensor descriptor type. Everything else remains unchanged.
Example 1:
```
#lo0 = #xegpu.layout<wi_layout = [1, 8], wi_data = [1, 1]>
gpu.warp_execute_on_lane_0(%laneid) -> () {
...
xegpu.prefetch_nd %arg0 : !xegpu.tensor_desc<4x8xf32, #lo0>
}
```
To
```
%r:2 = gpu.warp_execute_on_lane_0(%laneid) -> (
!xegpu.tensor_desc<4x8xf32, #lo0>) {
gpu.yield %arg0: !xegpu.tensor_desc<4x8xf32, #lo0>
}
%1 = unrealized_conversion_cast %r#0: !xegpu.tensor_desc<4x8xf32,
#lo0> -> !xegpu.tensor_desc<4x8xf32>
xegpu.prefetch_nd %0 : !xegpu.tensor_desc<4x8xf32>
```
Example 2:
```
#lo0 = #xegpu.layout<wi_layout = [1, 8], wi_data = [1, 1]>
%r = gpu.warp_execute_on_lane_0(%laneid) ->
(!xegpu.tensor_desc<4x8xf32, #lo0>) {
...
%update = xegpu.update_nd_offset %arg0, [%c32, %c16]:
!xegpu.tensor_desc<4x8xf32, #lo0>
gpu.yield %update
}
...
```
To
```
%r:2 = gpu.warp_execute_on_lane_0(%laneid) -> (vector<4x1xf32>,
!xegpu.tensor_desc<4x8xf32, #lo0>) {
...
%dead = xegpu.update_nd_offset %arg0, [%c32, %c16]:
!xegpu.tensor_desc<4x8xf32, #lo0> gpu.yield %dead, %arg0
gup.yield %dead, %arg0, %c32, %c16
}
%0 = xegpu.unrealized_conversion_cast %r#1: !xegpu.tensor_desc<4x8xf32,
#lo0> -> !xegpu.tensor_desc<4x8xf32>
%1 = xegpu.update_nd_offset %0, [%c32, %c16]:
!xegpu.tensor_desc<4x8xf32>
...
```
Commit: c82e2f5c9ed08a270a1ec60bf7313af9c236ab98
https://github.com/llvm/llvm-project/commit/c82e2f5c9ed08a270a1ec60bf7313af9c236ab98
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Move VPPhiAccessors definition. (NFC)
Move up definition to allow re-use by additional recipes.
Commit: 45d493b680e3e79e4e9c19d665df83823c52a73a
https://github.com/llvm/llvm-project/commit/45d493b680e3e79e4e9c19d665df83823c52a73a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/expected.h
M libcxx/include/__locale
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__split_buffer
A libcxx/include/__type_traits/is_replaceable.h
M libcxx/include/__utility/pair.h
M libcxx/include/__vector/vector.h
M libcxx/include/array
M libcxx/include/deque
M libcxx/include/module.modulemap.in
M libcxx/include/optional
M libcxx/include/string
M libcxx/include/tuple
M libcxx/include/variant
A libcxx/test/libcxx/type_traits/is_replaceable.compile.pass.cpp
Log Message:
-----------
[libc++] Add the __is_replaceable type trait (#132408)
That type trait represents whether move-assigning an object is
equivalent to destroying it and then move-constructing a new one from
the same argument. This will be useful in a few places where we may want
to destroy + construct instead of doing an assignment, in particular
when implementing some container operations in terms of relocation.
This is effectively adding a library emulation of P2786R12's
is_replaceable trait, similarly to what we do for trivial relocation.
Eventually, we can replace this library emulation by the real
compiler-backed trait.
This is building towards #129328.
Commit: dbe320efa19e52351a4819fc50d62219852cd381
https://github.com/llvm/llvm-project/commit/dbe320efa19e52351a4819fc50d62219852cd381
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/InterfaceExportAnnotations.rst
Log Message:
-----------
[llvm] minor revisions to export annotation macro docs (#138761)
## Purpose
Make some minor tweaks and clarifications to the `LLVM_ABI` export
annotation docs.
## Overview
1. Minor cleanup on wording throughout
2. Clarification around class-level annotation requirements to export
vtable
## Validation
Manually inspected docs on [my fork
here](https://github.com/andrurogerz/llvm-project/blob/llvm-export-annotation-doc-update/llvm/docs/InterfaceExportAnnotations.rst).
Commit: f39ac3f569519a6f6c1618b23e20d47a74abef1e
https://github.com/llvm/llvm-project/commit/f39ac3f569519a6f6c1618b23e20d47a74abef1e
Author: Hui <hui.xie1990 at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
A libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert.temporary.pass.cpp
A libcxx/test/libcxx/containers/container.adaptors/flat.set/insert.temporary.pass.cpp
A libcxx/test/libcxx/containers/container.adaptors/flat_helpers.h
Log Message:
-----------
[libc++] Add test for flat_set::insert not creating temporaries (#138387)
Fixes #119016
Commit: 741fef3a445339523500f614e0f752b9a74517a6
https://github.com/llvm/llvm-project/commit/741fef3a445339523500f614e0f752b9a74517a6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 45d493b680e3
Commit: 948bffa951cf143da5f4caa461b25ce76fa137d0
https://github.com/llvm/llvm-project/commit/948bffa951cf143da5f4caa461b25ce76fa137d0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M libcxx/include/__math/copysign.h
M libcxx/include/__math/exponential_functions.h
M libcxx/include/__math/fdim.h
M libcxx/include/__math/fma.h
M libcxx/include/__math/hypot.h
M libcxx/include/__math/inverse_trigonometric_functions.h
M libcxx/include/__math/min_max.h
M libcxx/include/__math/modulo.h
M libcxx/include/__math/remainder.h
M libcxx/include/__math/rounding_functions.h
M libcxx/include/__math/traits.h
M libcxx/include/__type_traits/promote.h
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp
Log Message:
-----------
[libc++] Simplify __promote (#136101)
This avoids instantiating an extra class for every variant `__promote`
is used in.
Commit: a76cf062a57097ad7971325551854bd5f3d38d94
https://github.com/llvm/llvm-project/commit/a76cf062a57097ad7971325551854bd5f3d38d94
Author: Florian Mayer <fmayer at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
A llvm/test/Instrumentation/HWAddressSanitizer/personality-bti.ll
Log Message:
-----------
[HWASan] fix missing BTI attribute on personality function thunks (#139138)
This used to work because the BTI attribute was taken from the module in
the CodeGen.
e15d67cfc2e5775cc79281aa860f3ad3be628f39 changed that to actually look
at the function attributes. This led to crashes for BTI, because we did
not emit the proper landing pads for the thunk.
Commit: 2693a715bf2b343d6d4b196c6fb15474d3bc1377
https://github.com/llvm/llvm-project/commit/2693a715bf2b343d6d4b196c6fb15474d3bc1377
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Port 515b4a4fdd7ac97373b68850a2ffa72e2b8e9178 (#139155)
Commit: 47fb5bd494a9dd391abceafddb872e01a7d3492b
https://github.com/llvm/llvm-project/commit/47fb5bd494a9dd391abceafddb872e01a7d3492b
Author: Reid Kleckner <rnk at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M clang/unittests/Support/TimeProfilerTest.cpp
Log Message:
-----------
[clang] Deflake the TimeProfile support tests (#138613)
These tests have been flaky since they were merged into the
AllClangUnitTests binary, but the flakiness is inherent to the nature of
timer-based tests.
Commit: 03896403d3bf330c8163aa9ae3fe2aa284e273be
https://github.com/llvm/llvm-project/commit/03896403d3bf330c8163aa9ae3fe2aa284e273be
Author: John Harrison <harjohn at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/RestartRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Migrate attach to typed RequestHandler. (#137911)
This updates the `attach` request to the typed
`RequestHandler<protocol::AttachRequestArguments,
protocol::AttachResponse>`.
Added a few more overlapping configurations to
`lldb_dap::protocol::Configuration` that are shared between launching
and attaching.
There may be some additional code we could clean-up that is no longer
referenced now that this has migrated to use well defined types.
Commit: 0df1a52852f570fb72c25f88f94f9b51e4689f1d
https://github.com/llvm/llvm-project/commit/0df1a52852f570fb72c25f88f94f9b51e4689f1d
Author: Ahmed Bougacha <ahmed at bougacha.org>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
A llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll
Log Message:
-----------
[AArch64][FastISel] Fallback on atomic stlr/cas with non-reg operands. (#133987)
This has been a latent bug for almost 10 years, but is relatively hard
to trigger, needing an address operand that isn't handled by
getRegForValue (in the test here, constexpr casts). When that happens,
it returns 0, which FastISel happily uses as a register operand, all the
way to asm, where we either get a crash on an invalid register, or a
silently corrupt instruction.
Unfortunately, FastISel is still enabled at -O0 for at least
ILP32/arm64_32.
Commit: 92d949229273a7c1dfb923a2b8fbac92fae04fd5
https://github.com/llvm/llvm-project/commit/92d949229273a7c1dfb923a2b8fbac92fae04fd5
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Address post-commit review feedback on 1ac489c8e
As noted by @s-barannikov, the last argument wasn't reflected in the type
profile for the SDNode, nor was it being used by the patterns.
Commit: 06d6623bc304d5fc2fe11b80b62b4c5d10f9eaa1
https://github.com/llvm/llvm-project/commit/06d6623bc304d5fc2fe11b80b62b4c5d10f9eaa1
Author: David Salinas <dsalinas at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/docs/CommandGuide/llvm-objdump.rst
A llvm/include/llvm/Object/OffloadBundle.h
M llvm/lib/Object/CMakeLists.txt
A llvm/lib/Object/OffloadBundle.cpp
A llvm/test/tools/llvm-objdump/Offloading/fatbin.test
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/OffloadDump.h
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/Object/CMakeLists.txt
A llvm/unittests/Object/OffloadingBundleTest.cpp
Log Message:
-----------
[llvm-objdump] Add support for HIP offload bundles (#114834)
Utilize the new extensions to the LLVM Offloading API to extend to
llvm-objdump to handle dumping fatbin offload bundles generated by HIP.
This extension to llvm-objdump adds the option --offload-fatbin.
Specifying this option will take the input object/executable and extract
all offload fatbin bundle entries into distinct code object files with
names reflecting the source file name combined with the Bundle Entry ID.
Users can also use the --arch-name option to filter offload fatbin
bundle entries by their target triple.
---------
Co-authored-by: dsalinas <dsalinas at MKM-L1-DSALINAS.amd.com>
Commit: 13b2f7c78574ce484c38d82769f8d4168cabd6ed
https://github.com/llvm/llvm-project/commit/13b2f7c78574ce484c38d82769f8d4168cabd6ed
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] add fake16 to gisel test (#138588)
This is a NFC patch.
Add '-mattr=-real-true16' to gfx11/gfx12 test.
GISEL is not fully supported in true16 mode yet. However we might want
to turn on true16 mode for SDAG as default first. This patch is
preparing for this mode shift in the short future so we can have a small
patch to turn it on
Commit: c336bd74fa47c5cd57b7ea9aaa1e78d3cc1cb522
https://github.com/llvm/llvm-project/commit/c336bd74fa47c5cd57b7ea9aaa1e78d3cc1cb522
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] added missing testlines for t16 test (#135823)
This is a NFC patch.
Update testlines for true16 mc inst including:
v_min_num_f16
v_max_num_f16
v_cvt_f16_f32
v_cmp_tru_f16
v_cmpx_tru_f16
v_min_num_f16
v_max_num_f16
v_cvt_pknorm_i16_f16
v_med3_f16
The functional change is done, but these are testlines that are not yet
up-to-date
Commit: 8af71bf5a8312276d800107d338ba336538106bc
https://github.com/llvm/llvm-project/commit/8af71bf5a8312276d800107d338ba336538106bc
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M CONTRIBUTING.md
M bolt/Maintainers.txt
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/BinarySection.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Passes/PatchEntries.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/AArch64/lite-mode.s
M bolt/unittests/Core/BinaryContext.cpp
M clang-tools-extra/Maintainers.txt
M clang/Maintainers.rst
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclOpenACC.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Lex/HLSLRootSignatureTokenKinds.def
M clang/include/clang/Parse/ParseHLSLRootSignature.h
M clang/include/clang/Sema/ParsedTemplate.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclObjC.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/ProfileList.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/Job.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Arch/Mips.cpp
M clang/lib/Driver/ToolChains/Arch/X86.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Lex/InitHeaderSearch.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CIR/CodeGen/vector-ext.cpp
M clang/test/CIR/CodeGen/vector.cpp
M clang/test/CIR/IR/vector.cir
M clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
M clang/test/CodeGen/ms_abi.c
M clang/test/CodeGen/profile-filter.c
M clang/test/CodeGen/sysv_abi.c
M clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/max-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/min-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl
M clang/test/CodeGenObjCXX/arc-rv-attr.mm
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
M clang/test/CodeGenOpenCL/blocks.cl
M clang/test/CodeGenOpenCL/builtins-alloca.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/implicit-addrspacecast-function-parameter.cl
A clang/test/Driver/Inputs/DriverKit19.0.sdk/System/DriverKit/System/Library/SubFrameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/Library/Frameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/System/Library/Frameworks/.keep
A clang/test/Driver/Inputs/MacOSX15.1.sdk/System/Library/SubFrameworks/.keep
A clang/test/Driver/darwin-framework-search-paths.c
R clang/test/Driver/darwin-subframeworks.c
M clang/test/Driver/driverkit-path.c
M clang/test/Driver/fprofile-generate-cold-function-coverage.c
R clang/test/Driver/mips-cpus.c
M clang/test/Driver/x86-mabi.c
M clang/test/Index/pipe-size.cl
M clang/test/Lexer/char8_t.cpp
M clang/test/Modules/Inputs/submodules/module.modulemap
M clang/test/Modules/missing-header.m
R clang/test/Preprocessor/cuda-macos-includes.cu
M clang/test/Sema/callingconv-ms_abi.c
M clang/test/Sema/varargs-win64.c
A clang/test/SemaCUDA/overloaded-builtin.cu
M clang/test/SemaCXX/attr-trivial-abi.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/tools/libclang/CXIndexDataConsumer.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Frontend/CMakeLists.txt
A clang/unittests/Frontend/SearchPathTest.cpp
M clang/unittests/Lex/LexHLSLRootSignatureTest.cpp
M clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
M clang/www/menu.html.incl
M compiler-rt/lib/builtins/CMakeLists.txt
M flang-rt/CODE_OWNERS.TXT
M flang/docs/OpenMPSupport.md
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
M flang/test/Fir/do_concurrent.fir
M flang/test/Fir/invalid.fir
M flang/test/Lower/HLFIR/designators-component-ref.f90
A flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/allocate-source-allocatables-2.f90
M flang/test/Lower/allocate-source-allocatables.f90
M flang/test/Lower/allocate-source-pointers.f90
A flang/test/Lower/volatile-allocatable.f90
M flang/test/Transforms/DoConcurrent/basic_device.mlir
M flang/test/Transforms/DoConcurrent/basic_host.f90
M flang/test/Transforms/DoConcurrent/basic_host.mlir
M flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90
R flang/test/Transforms/DoConcurrent/loop_nest_test.f90
M flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90
M flang/test/Transforms/DoConcurrent/non_const_bounds.f90
M flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90
M libcxx/include/CMakeLists.txt
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/expected.h
M libcxx/include/__locale
M libcxx/include/__math/copysign.h
M libcxx/include/__math/exponential_functions.h
M libcxx/include/__math/fdim.h
M libcxx/include/__math/fma.h
M libcxx/include/__math/hypot.h
M libcxx/include/__math/inverse_trigonometric_functions.h
M libcxx/include/__math/min_max.h
M libcxx/include/__math/modulo.h
M libcxx/include/__math/remainder.h
M libcxx/include/__math/rounding_functions.h
M libcxx/include/__math/traits.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__split_buffer
A libcxx/include/__type_traits/is_replaceable.h
M libcxx/include/__type_traits/promote.h
M libcxx/include/__utility/pair.h
M libcxx/include/__vector/vector.h
M libcxx/include/array
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/include/deque
M libcxx/include/module.modulemap.in
M libcxx/include/optional
M libcxx/include/string
M libcxx/include/tuple
M libcxx/include/variant
A libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert.temporary.pass.cpp
A libcxx/test/libcxx/containers/container.adaptors/flat.set/insert.temporary.pass.cpp
A libcxx/test/libcxx/containers/container.adaptors/flat_helpers.h
M libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp
A libcxx/test/libcxx/type_traits/is_replaceable.compile.pass.cpp
M libcxx/utils/ci/BOT_OWNERS.txt
M lld/ELF/Options.td
M lldb/include/lldb/API/SBThreadPlan.h
M lldb/include/lldb/Core/SourceManager.h
M lldb/include/lldb/DataFormatters/FormattersHelpers.h
M lldb/source/API/SBThreadPlan.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxProxyArray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSliceArray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxValarray.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppTuple.cpp
M lldb/source/Plugins/Language/ObjC/NSArray.cpp
M lldb/source/Plugins/Language/ObjC/NSDictionary.cpp
M lldb/source/Plugins/Language/ObjC/NSIndexPath.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Utility/Checksum.cpp
M lldb/test/API/functionalities/statusline/TestStatusline.py
M lldb/test/API/functionalities/step_scripted/Steps.py
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
M lldb/test/API/functionalities/step_scripted/main.c
A lldb/test/API/lang/cpp/type_lookup_anon_struct/Makefile
A lldb/test/API/lang/cpp/type_lookup_anon_struct/TestCppTypeLookupAnonStruct.py
A lldb/test/API/lang/cpp/type_lookup_anon_struct/main.cpp
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attachByPortNum.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
M lldb/test/API/tools/lldb-dap/commands/TestDAP_commands.py
M lldb/test/API/tools/lldb-dap/disassemble/TestDAP_disassemble.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
A lldb/test/Shell/Commands/command-list-reach-beginning-of-file.test
A lldb/test/Shell/Commands/command-list-reach-end-of-file.test
M lldb/test/Shell/Expr/TestProcessModificationIdOnExpr.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ContinueRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/RestartRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/package.json
M llvm/CREDITS.TXT
M llvm/Maintainers.md
M llvm/docs/CodeOfConduct.rst
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/docs/DiscourseMigrationGuide.md
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/InterfaceExportAnnotations.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/UndefinedBehavior.rst
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
R llvm/include/llvm/ExecutionEngine/JITLink/ELF_i386.h
A llvm/include/llvm/ExecutionEngine/JITLink/ELF_x86.h
R llvm/include/llvm/ExecutionEngine/JITLink/i386.h
A llvm/include/llvm/ExecutionEngine/JITLink/x86.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/Use.h
M llvm/include/llvm/IR/Value.h
A llvm/include/llvm/Object/OffloadBundle.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/lib/Analysis/AssumeBundleQueries.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TypeMetadataUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/WinEHPrepare.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/DebugInfo/MSF/MSFBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
R llvm/lib/ExecutionEngine/JITLink/ELF_i386.cpp
A llvm/lib/ExecutionEngine/JITLink/ELF_x86.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
R llvm/lib/ExecutionEngine/JITLink/i386.cpp
A llvm/lib/ExecutionEngine/JITLink/x86.cpp
M llvm/lib/Frontend/OpenMP/OMP.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AttributeImpl.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Use.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCSymbol.cpp
M llvm/lib/Object/CMakeLists.txt
A llvm/lib/Object/OffloadBundle.cpp
M llvm/lib/ObjectYAML/MinidumpEmitter.cpp
M llvm/lib/Support/FoldingSet.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.h
A llvm/lib/Target/ARC/ARCSelectionDAGInfo.cpp
A llvm/lib/Target/ARC/ARCSelectionDAGInfo.h
M llvm/lib/Target/ARC/ARCSubtarget.cpp
M llvm/lib/Target/ARC/ARCSubtarget.h
M llvm/lib/Target/ARC/CMakeLists.txt
M llvm/lib/Target/CSKY/CMakeLists.txt
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.h
A llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.cpp
A llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.h
M llvm/lib/Target/CSKY/CSKYSubtarget.cpp
M llvm/lib/Target/CSKY/CSKYSubtarget.h
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/Lanai/CMakeLists.txt
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.h
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Analysis/MemorySSA/nondeterminism.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
A llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll
A llvm/test/CodeGen/AArch64/icmp-or-load.ll
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
M llvm/test/CodeGen/AArch64/str-narrow-zero-merge.mir
A llvm/test/CodeGen/AArch64/sve-bf16-compares.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
A llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
A llvm/test/CodeGen/DirectX/is_fpclass.ll
A llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
M llvm/test/CodeGen/Mips/msa/arithmetic.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-store.ll
M llvm/test/CodeGen/WinEH/wineh-asm.ll
A llvm/test/CodeGen/WinEH/wineh-asm2.ll
R llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll
M llvm/test/CodeGen/X86/asm-modifier-macho.ll
A llvm/test/CodeGen/X86/asm-modifier-pic.ll
M llvm/test/CodeGen/X86/asm-modifier.ll
A llvm/test/CodeGen/X86/codegen-no-uselist-constantdata.ll
R llvm/test/CodeGen/X86/pr19752.ll
A llvm/test/DebugInfo/Generic/discriminant-member.ll
A llvm/test/DebugInfo/KeyInstructions/X86/cgp-break-critical-edge.ll
A llvm/test/DebugInfo/KeyInstructions/X86/lit.local.cfg
A llvm/test/DebugInfo/KeyInstructions/X86/parse.mir
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
R llvm/test/ExecutionEngine/JITLink/i386/ELF_external_to_absolute_conversion.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_absolute_relocations_16.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_absolute_relocations_32.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_minimal.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_pc_relative_relocations_32.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_small_pic_relocations_got.s
R llvm/test/ExecutionEngine/JITLink/i386/ELF_i386_small_pic_relocations_plt.s
R llvm/test/ExecutionEngine/JITLink/i386/lit.local.cfg
A llvm/test/ExecutionEngine/JITLink/x86/ELF_external_to_absolute_conversion.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_absolute_relocations_16.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_absolute_relocations_32.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_minimal.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_pc_relative_relocations_32.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_small_pic_relocations_got.s
A llvm/test/ExecutionEngine/JITLink/x86/ELF_x86_small_pic_relocations_plt.s
A llvm/test/ExecutionEngine/JITLink/x86/lit.local.cfg
A llvm/test/Instrumentation/HWAddressSanitizer/personality-bti.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
A llvm/test/MC/AsmParser/quoted.s
M llvm/test/MC/COFF/safeseh.s
M llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
M llvm/test/MC/ELF/symbol-names.s
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/cc-assign-to-reg-tuple.td
A llvm/test/Transforms/CodeGenPrepare/X86/split-dbg.ll
A llvm/test/Transforms/CorrelatedValuePropagation/no-uselist-constantdata-regression.ll
A llvm/test/Transforms/InstCombine/fold-phi-arg-gep-to-phi-negative.ll
A llvm/test/Transforms/InstCombine/or-or-combine.ll
M llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
M llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
A llvm/test/Transforms/LoopVectorize/pr125278.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
A llvm/test/tools/llvm-diff/uselistorder-issue58629-gv.ll
M llvm/test/tools/llvm-diff/uselistorder-issue58629.ll
A llvm/test/tools/llvm-objdump/Offloading/fatbin.test
M llvm/test/tools/llvm-reduce/bitcode-uselistorder.ll
M llvm/test/tools/llvm-reduce/uselistorder-invalid-ir-output.ll
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/OffloadDump.h
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/verify-uselistorder/verify-uselistorder.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
M llvm/unittests/ExecutionEngine/JITLink/StubsTests.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
M llvm/unittests/IR/ConstantsTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/unittests/Object/CMakeLists.txt
A llvm/unittests/Object/OffloadingBundleTest.cpp
M llvm/unittests/Support/TrailingObjectsTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/gn/secondary/clang/unittests/Frontend/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Lanai/BUILD.gn
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinAttributeInterfaces.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/Support/StorageUniquer.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
M mlir/lib/Dialect/Affine/Analysis/NestedMatcher.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/IR/AffineMapDetail.h
M mlir/lib/IR/Location.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Tools/PDLL/AST/Nodes.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/AMDGPU/transfer-read-to-load.mlir
M mlir/test/Dialect/Affine/raise-memref.mlir
M mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
M mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
A mlir/test/Target/LLVMIR/openmp-cancel-distribute-parallel-loop.mlir
M mlir/test/Target/LLVMIR/openmp-cancel.mlir
A mlir/test/Target/LLVMIR/openmp-cancellation-point.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M polly/lib/Support/ScopHelper.cpp
M utils/bazel/.bazelrc
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/55f3a0a8f76d...8af71bf5a831
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