[all-commits] [llvm/llvm-project] 0df1a5: [AArch64][FastISel] Fallback on atomic stlr/cas wi...

[Ahmed Bougacha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0df1a52852f570fb72c25f88f94f9b51e4689f1d
      https://github.com/llvm/llvm-project/commit/0df1a52852f570fb72c25f88f94f9b51e4689f1d
  Author: Ahmed Bougacha <ahmed at bougacha.org>
  Date:   2025-05-08 (Thu, 08 May 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FastISel.cpp
    A llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll

  Log Message:
  -----------
  [AArch64][FastISel] Fallback on atomic stlr/cas with non-reg operands. (#133987)

This has been a latent bug for almost 10 years, but is relatively hard
to trigger, needing an address operand that isn't handled by
getRegForValue (in the test here, constexpr casts). When that happens,
it returns 0, which FastISel happily uses as a register operand, all the
way to asm, where we either get a crash on an invalid register, or a
silently corrupt instruction.

Unfortunately, FastISel is still enabled at -O0 for at least
ILP32/arm64_32.



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