[all-commits] [llvm/llvm-project] 808a5f: [RISCV] Remove`riscv.segN.load/store` in favor of ...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 808a5f15d7855f78a837c20e866cf4d0b1b90ab2
      https://github.com/llvm/llvm-project/commit/808a5f15d7855f78a837c20e866cf4d0b1b90ab2
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-05-08 (Thu, 08 May 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-store.ll
    M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
    M llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

  Log Message:
  -----------
  [RISCV] Remove`riscv.segN.load/store` in favor of their mask variants (#137045)

RISCVVectorPeepholePass would replace instructions with all-ones mask
with their unmask variant, so there isn't really a point to keep
separate versions of intrinsics.

Note that `riscv.segN.load/store.mask` does not take pointer type (i.e.
address space) as part of its overloading type signature, because RISC-V
doesn't really use address spaces other than the default one.



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