[all-commits] [llvm/llvm-project] 63fcce: [IA][RISCV] Add support for vp.load/vp.store with ...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 63fcce6611483658e310741b49460ff6350e9bc0
      https://github.com/llvm/llvm-project/commit/63fcce6611483658e310741b49460ff6350e9bc0
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-05-07 (Wed, 07 May 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [IA][RISCV] Add support for vp.load/vp.store with shufflevector (#135445)

Teach InterleavedAccessPass to recognize vp.load + shufflevector and
shufflevector + vp.store. Though this patch only adds RISC-V support to
actually lower this pattern. The vp.load/vp.store in this pattern
require constant mask.



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