[all-commits] [llvm/llvm-project] 1ac489: [RISCV] Initial codegen support for zvqdotq extens...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ac489c8e38ecaeccba7d8826273395eaba2db6c
      https://github.com/llvm/llvm-project/commit/1ac489c8e38ecaeccba7d8826273395eaba2db6c
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-05-07 (Wed, 07 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll

  Log Message:
  -----------
  [RISCV] Initial codegen support for zvqdotq extension (#137039)

This patch adds pattern matching for the basic usages of the dot product
instructions introduced by the experimental zvqdotq extension. It
specifically only handles the case where the pattern is feeding a i32
sum reduction as we need to reassociate the reduction tree to use these
instructions.

The vecreduce_add (sext) and vecreduce_add (zext) cases are included
mostly to exercise the VX matchers. For the generic matching, we fail to
match due to an order of combine issue which results in the bitcast
being separated from the splat.

I chose to do this lowering as an early combine so as to avoid having to
integrate the entire logic into the reduction lowering flow. In
particular, that would get a lot more complicated as we extend this to
handle add-trees feeding the reductions.



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