[all-commits] [llvm/llvm-project] 7f46c6: [Intrinsics][AArch64] Add intrinsic to mask off al...
Sam Tebbs via All-commits
all-commits at lists.llvm.org
Wed May 7 06:00:43 PDT 2025
Branch: refs/heads/users/SamTebbs33/alias-intrinsic
Home: https://github.com/llvm/llvm-project
Commit: 7f46c67016cd09ab864dbe24158a880fbdac1f44
https://github.com/llvm/llvm-project/commit/7f46c67016cd09ab864dbe24158a880fbdac1f44
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/alias_mask.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
[Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes
It can be unsafe to load a vector from an address and write a vector to
an address if those two addresses have overlapping lanes within a
vectorised loop iteration.
This PR adds an intrinsic designed to create a mask with lanes disabled
if they overlap between the two pointer arguments, so that only safe
lanes are loaded, operated on and stored.
Along with the two pointer parameters, the intrinsic also takes an
immediate that represents the size in bytes of the vector element
types, as well as an immediate i1 that is true if there is a write
after-read-hazard or false if there is a read-after-write hazard.
This will be used by #100579 and replaces the existing lowering for
whilewr since that isn't needed now we have the intrinsic.
Commit: 584cf923cea0b542e9d6e4ec7db2e8387e1e4f2a
https://github.com/llvm/llvm-project/commit/584cf923cea0b542e9d6e4ec7db2e8387e1e4f2a
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rework lowering location
Commit: fab768acbb98ced249f1135d968b0f2d80d6f34f
https://github.com/llvm/llvm-project/commit/fab768acbb98ced249f1135d968b0f2d80d6f34f
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
Log Message:
-----------
Fix ISD node name string and remove shouldExpand function
Commit: f6718e39b220f5114a886b799cc5564b42a485e2
https://github.com/llvm/llvm-project/commit/f6718e39b220f5114a886b799cc5564b42a485e2
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Format
Commit: 5b7fa23ca08704c57f51d03894b51a929e9b6588
https://github.com/llvm/llvm-project/commit/5b7fa23ca08704c57f51d03894b51a929e9b6588
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Log Message:
-----------
Move promote case
Commit: 9f979d1a67b8587e3abcf1b02dd89aa8046f03fe
https://github.com/llvm/llvm-project/commit/9f979d1a67b8587e3abcf1b02dd89aa8046f03fe
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Log Message:
-----------
Fix tablegen comment
Commit: f40e49de9a6425482f226ddc645ef577123bf012
https://github.com/llvm/llvm-project/commit/f40e49de9a6425482f226ddc645ef577123bf012
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Log Message:
-----------
Remove DAGTypeLegalizer::
Commit: dee9e98ce3be695b7a43d9870d27e61d56f9d7e3
https://github.com/llvm/llvm-project/commit/dee9e98ce3be695b7a43d9870d27e61d56f9d7e3
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Use getConstantOperandVal
Commit: e73829577008188f3512f6e00292f86a4f03f371
https://github.com/llvm/llvm-project/commit/e73829577008188f3512f6e00292f86a4f03f371
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Remove isPredicateCCSettingOp case
Commit: 12b3bf37a983ef0d07bc8bf12ee39a4c609f35bc
https://github.com/llvm/llvm-project/commit/12b3bf37a983ef0d07bc8bf12ee39a4c609f35bc
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Remove overloads for pointer and element size parameters
Commit: bbb058bcb6513cd26d456e60b0c83d558546e0cd
https://github.com/llvm/llvm-project/commit/bbb058bcb6513cd26d456e60b0c83d558546e0cd
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Clarify elementSize and writeAfterRead = 0
Commit: c4e20ea4d84b1640837662c82e8b618eb79b2f7b
https://github.com/llvm/llvm-project/commit/c4e20ea4d84b1640837662c82e8b618eb79b2f7b
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Add i=0 to VF-1
Commit: 160d3735c6f50c7329a7f4b3395b7b68f4fb5d0a
https://github.com/llvm/llvm-project/commit/160d3735c6f50c7329a7f4b3395b7b68f4fb5d0a
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to get.nonalias.lane.mask
Commit: 7cd1f0d3a26d8efb70f3bc2ab10341528013c83b
https://github.com/llvm/llvm-project/commit/7cd1f0d3a26d8efb70f3bc2ab10341528013c83b
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Fix pointer types in example
Commit: 8e7c79ce6b36a5e1f437306c6e2cb8e2fcf635de
https://github.com/llvm/llvm-project/commit/8e7c79ce6b36a5e1f437306c6e2cb8e2fcf635de
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
Log Message:
-----------
Remove shouldExpandGetAliasLaneMask
Commit: 14e8bdd1f60aef28c58957427e0054d780ff5e73
https://github.com/llvm/llvm-project/commit/14e8bdd1f60aef28c58957427e0054d780ff5e73
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Lower to ISD node rather than intrinsic
Commit: 207ba59d895a828504820a5b1580b3bc8e1d402e
https://github.com/llvm/llvm-project/commit/207ba59d895a828504820a5b1580b3bc8e1d402e
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to noalias
Commit: 77a0d9d3ae35b47d91420fee50a1cbd427c6e9c8
https://github.com/llvm/llvm-project/commit/77a0d9d3ae35b47d91420fee50a1cbd427c6e9c8
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to loop.dependence.raw/war.mask
Commit: b74394c7804b2286e7a8072f74c794c4f48f4ce8
https://github.com/llvm/llvm-project/commit/b74394c7804b2286e7a8072f74c794c4f48f4ce8
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Rename in langref
Commit: 8822b8fcffab7a410341925a93afd3fbc56bbf37
https://github.com/llvm/llvm-project/commit/8822b8fcffab7a410341925a93afd3fbc56bbf37
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Reword argument description
Compare: https://github.com/llvm/llvm-project/compare/4c4ab8aeed1b...8822b8fcffab
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