[all-commits] [llvm/llvm-project] 4eac57: [RISCV] Add scheduler definitions for SpacemiT-X60...

[Mikhail R. Gadelha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4eac576654d857e2d8d59783b7eb2d70cb0675f9
      https://github.com/llvm/llvm-project/commit/4eac576654d857e2d8d59783b7eb2d70cb0675f9
  Author: Mikhail R. Gadelha <mikhail at igalia.com>
  Date:   2025-05-06 (Tue, 06 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
    A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
    A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
    A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s

  Log Message:
  -----------
  [RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)

This patch adds an initial scheduler model for the SpacemiT-X60,
including latency for scalar instructions only.

The scheduler is based on the documented characteristics of the C908,
which the SpacemiT-X60 is believed to be based on, and provides the
expected latency for several instructions. I ran a probe to confirm all
of these values and to get the latency of instructions not provided by
the C908 documentation (e.g., double floating-point instructions).

For load and store instructions, the C908 documentation says the latency
is \>= 3 for load and 1 for store. I tried a few combinations of values
until I got the current values of 5 and 3, which yield the best results.

Although the X60 does appear to support multiple issue for at least some
floating point instructions, this model assumes single issue as
increasing it reduces the gains below.

This patch gives a geomean improvement of ~4% on SPEC CPU 2017 for both
rva22u64 and rva22u64_v, with some benchmarks improving up to 18%
(508.namd_r). There were a couple of execution time regressions, but
only in noisy benchmarks (523.xalancbmk_r and 510.parest_r).

* rva22u64: https://lnt.lukelau.me/db_default/v4/nts/507?compare_to=405
(compares a55f7275 to the baseline 8286b804)
* rva22u64_v:
https://lnt.lukelau.me/db_default/v4/nts/474?compare_to=404 (compares
a55f7275 to the baseline 8286b804)

This initial scheduling model is strongly focused on providing
sufficient definitions to provide improved performance for the
SpacemiT-X60. Further incremental gains may be possible through a much
more detailed microarchitectural analysis, but that is left to future
work.

Further scheduling definitions for RVV can be added in a future PR.



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