[all-commits] [llvm/llvm-project] ca1ebf: [RISCV] Add processor definition for SiFive P870 (...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ca1ebff9decdd64804079a3e3ae62f613ca76a9e
      https://github.com/llvm/llvm-project/commit/ca1ebff9decdd64804079a3e3ae62f613ca76a9e
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-05-05 (Mon, 05 May 2025)

  Changed paths:
    A clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add processor definition for SiFive P870 (#137725)

SiFive P870 is a RVA23 compatible high-performance CPU:
https://www.sifive.com/cores/performance-p800

Scheduling model will be added in a follow-up PR.



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