[all-commits] [llvm/llvm-project] 0bd065: [AMDGPU] Extend test coverage for cross RC registe...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bd065dc943ff65e0749a9f2a7b7a672acd45193
      https://github.com/llvm/llvm-project/commit/0bd065dc943ff65e0749a9f2a7b7a672acd45193
  Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
  Date:   2025-05-05 (Mon, 05 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir

  Log Message:
  -----------
  [AMDGPU] Extend test coverage for cross RC register coalescing (#132137)

Add some test cases for subregister to subregister copies. Also add
cases where the register class is not required by the instruction.



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