[all-commits] [llvm/llvm-project] c22bc2: [MIPS] Reland Scheduling model for MIPS i6400 and ...

[Mallikarjuna Gouda via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c22bc215ac9496ee5f6e55ba0b0904dc825c6f56
      https://github.com/llvm/llvm-project/commit/c22bc215ac9496ee5f6e55ba0b0904dc825c6f56
  Author: Mallikarjuna Gouda <mgouda at mips.com>
  Date:   2025-05-04 (Sun, 04 May 2025)

  Changed paths:
    M llvm/lib/Target/Mips/Mips.td
    A llvm/lib/Target/Mips/MipsScheduleI6400.td
    A llvm/test/tools/llvm-mca/Mips/i6400.s
    A llvm/test/tools/llvm-mca/Mips/lit.local.cfg

  Log Message:
  -----------
  [MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) (#137984)

Relands #132704 with a fix in the testcase:
Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6
processor.

i6400 and i6500 share same instruction latencies.

CPU has following pipelines
  - Two ALUs
  - Multiply and Divide unit (MDU)
  - Branch Unit (CTU)
  - Load/Store Unit (LSU)
  - Short Floating-point Unit and
  - Long Floating-point Unit

Latency information is available at:

https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf



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