[all-commits] [llvm/llvm-project] 5060f0: [AArch64] Use pattern to select bf16 fpextend (#13...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5060f08c3a98c2e4976d7ec380d9d8ea1888a68c
      https://github.com/llvm/llvm-project/commit/5060f08c3a98c2e4976d7ec380d9d8ea1888a68c
  Author: John Brawn <john.brawn at arm.com>
  Date:   2025-05-02 (Fri, 02 May 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
    M llvm/test/CodeGen/AArch64/bf16-instructions.ll
    M llvm/test/CodeGen/AArch64/bf16_fast_math.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll

  Log Message:
  -----------
  [AArch64] Use pattern to select bf16 fpextend (#137212)

Currently bf16 fpextend is lowered to a vector shift. Instead leave it
as fpextend and have an instruction selection pattern which selects to a
shift later. Doing this means that DAGCombiner patterns for fpextend
will be applied, leading to better codegen. It also means that in some
situations we use a mov instruction where we previously have a dup
instruction, but I don't think this makes any difference.



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